Lines Matching refs:mc_reg_table
835 for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) { in cypress_convert_mc_reg_table_entry_to_smc()
837 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in cypress_convert_mc_reg_table_entry_to_smc()
841 if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0)) in cypress_convert_mc_reg_table_entry_to_smc()
844 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i], in cypress_convert_mc_reg_table_entry_to_smc()
846 eg_pi->mc_reg_table.last, in cypress_convert_mc_reg_table_entry_to_smc()
847 eg_pi->mc_reg_table.valid_flag); in cypress_convert_mc_reg_table_entry_to_smc()
852 SMC_Evergreen_MCRegisters *mc_reg_table) in cypress_convert_mc_reg_table_to_smc() argument
858 &mc_reg_table->data[2]); in cypress_convert_mc_reg_table_to_smc()
861 &mc_reg_table->data[3]); in cypress_convert_mc_reg_table_to_smc()
864 &mc_reg_table->data[4]); in cypress_convert_mc_reg_table_to_smc()
890 SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; in cypress_upload_mc_reg_table() local
893 cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table); in cypress_upload_mc_reg_table()
899 (u8 *)&mc_reg_table.data[2], in cypress_upload_mc_reg_table()
949 SMC_Evergreen_MCRegisters *mc_reg_table) in cypress_populate_mc_reg_addresses() argument
954 for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) { in cypress_populate_mc_reg_addresses()
955 if (eg_pi->mc_reg_table.valid_flag & (1 << j)) { in cypress_populate_mc_reg_addresses()
956 mc_reg_table->address[i].s0 = in cypress_populate_mc_reg_addresses()
957 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0); in cypress_populate_mc_reg_addresses()
958 mc_reg_table->address[i].s1 = in cypress_populate_mc_reg_addresses()
959 cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1); in cypress_populate_mc_reg_addresses()
964 mc_reg_table->last = (u8)i; in cypress_populate_mc_reg_addresses()
972 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
973 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
976 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
977 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
980 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2; in cypress_set_mc_reg_address_table()
981 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; in cypress_set_mc_reg_address_table()
984 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; in cypress_set_mc_reg_address_table()
985 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2; in cypress_set_mc_reg_address_table()
988 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2; in cypress_set_mc_reg_address_table()
989 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
992 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2; in cypress_set_mc_reg_address_table()
993 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
996 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; in cypress_set_mc_reg_address_table()
997 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2; in cypress_set_mc_reg_address_table()
1000 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2; in cypress_set_mc_reg_address_table()
1001 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
1004 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in cypress_set_mc_reg_address_table()
1005 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2; in cypress_set_mc_reg_address_table()
1008 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; in cypress_set_mc_reg_address_table()
1009 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2; in cypress_set_mc_reg_address_table()
1012 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; in cypress_set_mc_reg_address_table()
1013 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2; in cypress_set_mc_reg_address_table()
1016 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2; in cypress_set_mc_reg_address_table()
1017 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2; in cypress_set_mc_reg_address_table()
1020 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2; in cypress_set_mc_reg_address_table()
1021 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2; in cypress_set_mc_reg_address_table()
1024 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2; in cypress_set_mc_reg_address_table()
1025 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2; in cypress_set_mc_reg_address_table()
1028 eg_pi->mc_reg_table.last = (u8)i; in cypress_set_mc_reg_address_table()
1037 for (i = 0; i < eg_pi->mc_reg_table.last; i++) in cypress_retrieve_ac_timing_for_one_entry()
1039 RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); in cypress_retrieve_ac_timing_for_one_entry()
1050 eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max = in cypress_retrieve_ac_timing_for_all_ranges()
1054 &eg_pi->mc_reg_table.mc_reg_table_entry[i]); in cypress_retrieve_ac_timing_for_all_ranges()
1057 eg_pi->mc_reg_table.num_entries = range_table->num_entries; in cypress_retrieve_ac_timing_for_all_ranges()
1058 eg_pi->mc_reg_table.valid_flag = 0; in cypress_retrieve_ac_timing_for_all_ranges()
1060 for (i = 0; i < eg_pi->mc_reg_table.last; i++) { in cypress_retrieve_ac_timing_for_all_ranges()
1062 if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] != in cypress_retrieve_ac_timing_for_all_ranges()
1063 eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) { in cypress_retrieve_ac_timing_for_all_ranges()
1064 eg_pi->mc_reg_table.valid_flag |= (1 << i); in cypress_retrieve_ac_timing_for_all_ranges()
1172 for (i = 0; i < eg_pi->mc_reg_table.last; i++) { in cypress_copy_ac_timing_from_s1_to_s0()
1173 value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2); in cypress_copy_ac_timing_from_s1_to_s0()
1174 WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value); in cypress_copy_ac_timing_from_s1_to_s0()
1670 SMC_Evergreen_MCRegisters mc_reg_table = { 0 }; in cypress_populate_mc_reg_table() local
1675 cypress_populate_mc_reg_addresses(rdev, &mc_reg_table); in cypress_populate_mc_reg_table()
1679 &mc_reg_table.data[0]); in cypress_populate_mc_reg_table()
1681 cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0], in cypress_populate_mc_reg_table()
1682 &mc_reg_table.data[1], eg_pi->mc_reg_table.last, in cypress_populate_mc_reg_table()
1683 eg_pi->mc_reg_table.valid_flag); in cypress_populate_mc_reg_table()
1685 cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table); in cypress_populate_mc_reg_table()
1688 (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters), in cypress_populate_mc_reg_table()