2335 	u32 *tile = rdev->config.cik.tile_mode_array;  in cik_tiling_mode_table_init()
2336 	u32 *macrotile = rdev->config.cik.macrotile_mode_array;  in cik_tiling_mode_table_init()
2338 			ARRAY_SIZE(rdev->config.cik.tile_mode_array);  in cik_tiling_mode_table_init()
2340 			ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);  in cik_tiling_mode_table_init()
2343 	u32 num_rbs = rdev->config.cik.max_backends_per_se *  in cik_tiling_mode_table_init()
2344 		rdev->config.cik.max_shader_engines;  in cik_tiling_mode_table_init()
2346 	switch (rdev->config.cik.mem_row_size_in_kb) {  in cik_tiling_mode_table_init()
2359 	num_pipe_configs = rdev->config.cik.max_tile_pipes;  in cik_tiling_mode_table_init()
3143 	rdev->config.cik.backend_enable_mask = enabled_rbs;  in cik_setup_rb()
3192 		rdev->config.cik.max_shader_engines = 2;  in cik_gpu_init()
3193 		rdev->config.cik.max_tile_pipes = 4;  in cik_gpu_init()
3194 		rdev->config.cik.max_cu_per_sh = 7;  in cik_gpu_init()
3195 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3196 		rdev->config.cik.max_backends_per_se = 2;  in cik_gpu_init()
3197 		rdev->config.cik.max_texture_channel_caches = 4;  in cik_gpu_init()
3198 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3199 		rdev->config.cik.max_gs_threads = 32;  in cik_gpu_init()
3200 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3202 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3203 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3204 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3205 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3209 		rdev->config.cik.max_shader_engines = 4;  in cik_gpu_init()
3210 		rdev->config.cik.max_tile_pipes = 16;  in cik_gpu_init()
3211 		rdev->config.cik.max_cu_per_sh = 11;  in cik_gpu_init()
3212 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3213 		rdev->config.cik.max_backends_per_se = 4;  in cik_gpu_init()
3214 		rdev->config.cik.max_texture_channel_caches = 16;  in cik_gpu_init()
3215 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3216 		rdev->config.cik.max_gs_threads = 32;  in cik_gpu_init()
3217 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3219 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3220 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3221 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3222 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3226 		rdev->config.cik.max_shader_engines = 1;  in cik_gpu_init()
3227 		rdev->config.cik.max_tile_pipes = 4;  in cik_gpu_init()
3228 		rdev->config.cik.max_cu_per_sh = 8;  in cik_gpu_init()
3229 		rdev->config.cik.max_backends_per_se = 2;  in cik_gpu_init()
3230 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3231 		rdev->config.cik.max_texture_channel_caches = 4;  in cik_gpu_init()
3232 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3233 		rdev->config.cik.max_gs_threads = 16;  in cik_gpu_init()
3234 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3236 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3237 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3238 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3239 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3245 		rdev->config.cik.max_shader_engines = 1;  in cik_gpu_init()
3246 		rdev->config.cik.max_tile_pipes = 2;  in cik_gpu_init()
3247 		rdev->config.cik.max_cu_per_sh = 2;  in cik_gpu_init()
3248 		rdev->config.cik.max_sh_per_se = 1;  in cik_gpu_init()
3249 		rdev->config.cik.max_backends_per_se = 1;  in cik_gpu_init()
3250 		rdev->config.cik.max_texture_channel_caches = 2;  in cik_gpu_init()
3251 		rdev->config.cik.max_gprs = 256;  in cik_gpu_init()
3252 		rdev->config.cik.max_gs_threads = 16;  in cik_gpu_init()
3253 		rdev->config.cik.max_hw_contexts = 8;  in cik_gpu_init()
3255 		rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;  in cik_gpu_init()
3256 		rdev->config.cik.sc_prim_fifo_size_backend = 0x100;  in cik_gpu_init()
3257 		rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;  in cik_gpu_init()
3258 		rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;  in cik_gpu_init()
3281 	rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;  in cik_gpu_init()
3282 	rdev->config.cik.mem_max_burst_length_bytes = 256;  in cik_gpu_init()
3284 	rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;  in cik_gpu_init()
3285 	if (rdev->config.cik.mem_row_size_in_kb > 4)  in cik_gpu_init()
3286 		rdev->config.cik.mem_row_size_in_kb = 4;  in cik_gpu_init()
3288 	rdev->config.cik.shader_engine_tile_size = 32;  in cik_gpu_init()
3289 	rdev->config.cik.num_gpus = 1;  in cik_gpu_init()
3290 	rdev->config.cik.multi_gpu_tile_size = 64;  in cik_gpu_init()
3294 	switch (rdev->config.cik.mem_row_size_in_kb) {  in cik_gpu_init()
3314 	rdev->config.cik.tile_config = 0;  in cik_gpu_init()
3315 	switch (rdev->config.cik.num_tile_pipes) {  in cik_gpu_init()
3317 		rdev->config.cik.tile_config |= (0 << 0);  in cik_gpu_init()
3320 		rdev->config.cik.tile_config |= (1 << 0);  in cik_gpu_init()
3323 		rdev->config.cik.tile_config |= (2 << 0);  in cik_gpu_init()
3328 		rdev->config.cik.tile_config |= (3 << 0);  in cik_gpu_init()
3331 	rdev->config.cik.tile_config |=  in cik_gpu_init()
3333 	rdev->config.cik.tile_config |=  in cik_gpu_init()
3335 	rdev->config.cik.tile_config |=  in cik_gpu_init()
3349 	cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,  in cik_gpu_init()
3350 		     rdev->config.cik.max_sh_per_se,  in cik_gpu_init()
3351 		     rdev->config.cik.max_backends_per_se);  in cik_gpu_init()
3353 	rdev->config.cik.active_cus = 0;  in cik_gpu_init()
3354 	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {  in cik_gpu_init()
3355 		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {  in cik_gpu_init()
3356 			rdev->config.cik.active_cus +=  in cik_gpu_init()
3390 	WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |  in cik_gpu_init()
3391 				 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |  in cik_gpu_init()
3392 				 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |  in cik_gpu_init()
3393 				 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));  in cik_gpu_init()
3991 	WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);  in cik_cp_gfx_start()
5801 	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {  in cik_wait_for_rlc_serdes()
5802 		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {  in cik_wait_for_rlc_serdes()
6554 	for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {  in cik_get_cu_active_bitmap()
6568 	for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {  in cik_init_ao_cu_mask()
6569 		for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {  in cik_init_ao_cu_mask()
6573 			for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {  in cik_init_ao_cu_mask()
7304 	rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);  in cik_irq_ack()
7305 	rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);  in cik_irq_ack()
7306 	rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);  in cik_irq_ack()
7307 	rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);  in cik_irq_ack()
7308 	rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);  in cik_irq_ack()
7309 	rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);  in cik_irq_ack()
7310 	rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);  in cik_irq_ack()
7312 	rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7314 	rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7317 		rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7319 		rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7323 		rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7325 		rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS +  in cik_irq_ack()
7329 	if (rdev->irq.stat_regs.cik.d1grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7332 	if (rdev->irq.stat_regs.cik.d2grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7335 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)  in cik_irq_ack()
7337 	if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)  in cik_irq_ack()
7339 	if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)  in cik_irq_ack()
7341 	if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)  in cik_irq_ack()
7345 		if (rdev->irq.stat_regs.cik.d3grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7348 		if (rdev->irq.stat_regs.cik.d4grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7351 		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)  in cik_irq_ack()
7353 		if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)  in cik_irq_ack()
7355 		if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)  in cik_irq_ack()
7357 		if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)  in cik_irq_ack()
7362 		if (rdev->irq.stat_regs.cik.d5grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7365 		if (rdev->irq.stat_regs.cik.d6grph_int & GRPH_PFLIP_INT_OCCURRED)  in cik_irq_ack()
7368 		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)  in cik_irq_ack()
7370 		if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)  in cik_irq_ack()
7372 		if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)  in cik_irq_ack()
7374 		if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)  in cik_irq_ack()
7378 	if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {  in cik_irq_ack()
7383 	if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {  in cik_irq_ack()
7388 	if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {  in cik_irq_ack()
7393 	if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {  in cik_irq_ack()
7398 	if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {  in cik_irq_ack()
7403 	if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {  in cik_irq_ack()
7408 	if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT) {  in cik_irq_ack()
7413 	if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT) {  in cik_irq_ack()
7418 	if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT) {  in cik_irq_ack()
7423 	if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT) {  in cik_irq_ack()
7428 	if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT) {  in cik_irq_ack()
7433 	if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT) {  in cik_irq_ack()
7599 				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT))  in cik_irq_process()
7609 				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;  in cik_irq_process()
7614 				if (!(rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT))  in cik_irq_process()
7617 				rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;  in cik_irq_process()
7629 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT))  in cik_irq_process()
7639 				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;  in cik_irq_process()
7644 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT))  in cik_irq_process()
7647 				rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;  in cik_irq_process()
7659 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT))  in cik_irq_process()
7669 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;  in cik_irq_process()
7674 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT))  in cik_irq_process()
7677 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;  in cik_irq_process()
7689 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT))  in cik_irq_process()
7699 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;  in cik_irq_process()
7704 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT))  in cik_irq_process()
7707 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;  in cik_irq_process()
7719 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT))  in cik_irq_process()
7729 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;  in cik_irq_process()
7734 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT))  in cik_irq_process()
7737 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;  in cik_irq_process()
7749 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT))  in cik_irq_process()
7759 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;  in cik_irq_process()
7764 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT))  in cik_irq_process()
7767 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;  in cik_irq_process()
7789 				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT))  in cik_irq_process()
7792 				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;  in cik_irq_process()
7798 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT))  in cik_irq_process()
7801 				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;  in cik_irq_process()
7807 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT))  in cik_irq_process()
7810 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;  in cik_irq_process()
7816 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT))  in cik_irq_process()
7819 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;  in cik_irq_process()
7825 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT))  in cik_irq_process()
7828 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;  in cik_irq_process()
7834 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT))  in cik_irq_process()
7837 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;  in cik_irq_process()
7843 				if (!(rdev->irq.stat_regs.cik.disp_int & DC_HPD1_RX_INTERRUPT))  in cik_irq_process()
7846 				rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_RX_INTERRUPT;  in cik_irq_process()
7852 				if (!(rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_RX_INTERRUPT))  in cik_irq_process()
7855 				rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_RX_INTERRUPT;  in cik_irq_process()
7861 				if (!(rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_RX_INTERRUPT))  in cik_irq_process()
7864 				rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_RX_INTERRUPT;  in cik_irq_process()
7870 				if (!(rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_RX_INTERRUPT))  in cik_irq_process()
7873 				rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_RX_INTERRUPT;  in cik_irq_process()
7879 				if (!(rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_RX_INTERRUPT))  in cik_irq_process()
7882 				rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_RX_INTERRUPT;  in cik_irq_process()
7888 				if (!(rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_RX_INTERRUPT))  in cik_irq_process()
7891 				rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_RX_INTERRUPT;  in cik_irq_process()