Lines Matching refs:pi
198 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
200 return pi; in ci_get_pi()
212 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
222 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
228 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
232 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
236 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
246 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
250 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
252 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
253 pi->caps_cac = false; in ci_initialize_powertune_defaults()
254 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
255 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
256 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
257 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
259 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
260 pi->caps_cac = true; in ci_initialize_powertune_defaults()
262 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
264 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
265 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
266 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
277 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
278 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
279 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
280 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
306 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
307 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
310 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
313 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
314 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
321 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
322 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
324 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
325 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
326 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
327 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
334 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
335 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
339 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
340 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
342 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
349 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
350 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
357 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
358 pi->sram_end); in ci_populate_dw8()
362 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
369 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
376 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
384 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
385 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
386 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
408 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
409 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
416 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
417 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
418 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
425 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
426 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
433 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
434 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
435 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
446 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
448 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
481 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
485 if (pi->caps_power_containment) { in ci_populate_pm_base()
489 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
517 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
518 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
528 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
531 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
540 if (pi->caps_db_ramping) { in ci_do_enable_didt()
549 if (pi->caps_td_ramping) { in ci_do_enable_didt()
558 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
618 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
621 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
622 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
643 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
648 pi->power_containment_features = 0; in ci_enable_power_containment()
649 if (pi->caps_power_containment) { in ci_enable_power_containment()
650 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
655 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
658 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
663 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
666 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
676 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
683 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
684 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
687 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
690 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
692 pi->power_containment_features = 0; in ci_enable_power_containment()
701 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
705 if (pi->caps_cac) { in ci_enable_smc_cac()
710 pi->cac_enabled = false; in ci_enable_smc_cac()
712 pi->cac_enabled = true; in ci_enable_smc_cac()
714 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
716 pi->cac_enabled = false; in ci_enable_smc_cac()
726 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
729 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
744 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
752 if (pi->caps_power_containment) { in ci_power_control_set_level()
766 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
768 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
771 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
778 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
780 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
799 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
820 pi->battery_state = true; in ci_apply_state_adjust_rules()
822 pi->battery_state = false; in ci_apply_state_adjust_rules()
937 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
940 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
942 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
944 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
945 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
959 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
968 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
1021 pi->fan_table_start, in ci_thermal_setup_fan_table()
1024 pi->sram_end); in ci_thermal_setup_fan_table()
1036 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1039 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1058 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1065 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1069 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1106 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1111 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1151 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1154 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1215 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1218 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1220 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1224 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1226 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1284 struct ci_power_info *pi = ci_get_pi(rdev);
1287 pi->soft_regs_start + reg_offset,
1288 value, pi->sram_end);
1295 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1298 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1299 value, pi->sram_end); in ci_write_smc_soft_register()
1304 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1305 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1307 if (pi->caps_fps) { in ci_init_fps_limits()
1320 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1324 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1325 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1328 pi->dpm_table_start + in ci_update_sclk_t()
1331 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1340 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1345 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1346 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1354 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1355 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1356 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1366 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1367 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1368 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1371 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1372 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1373 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1382 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1417 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1433 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1436 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1437 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1438 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1441 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1442 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1443 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1456 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1459 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1462 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1463 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1469 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1470 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1476 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1482 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1486 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1492 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1510 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1516 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1528 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1553 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1564 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1567 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1570 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1571 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1577 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1578 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1589 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1602 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1634 struct ci_power_info *pi = ci_get_pi(rdev);
1646 if (pi->caps_automatic_dc_transition) {
1700 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1702 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1714 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1716 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1728 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1730 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1742 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1744 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1818 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1825 &tmp, pi->sram_end); in ci_process_firmware_header()
1829 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1834 &tmp, pi->sram_end); in ci_process_firmware_header()
1838 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1843 &tmp, pi->sram_end); in ci_process_firmware_header()
1847 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1852 &tmp, pi->sram_end); in ci_process_firmware_header()
1856 pi->fan_table_start = tmp; in ci_process_firmware_header()
1861 &tmp, pi->sram_end); in ci_process_firmware_header()
1865 pi->arb_table_start = tmp; in ci_process_firmware_header()
1872 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1874 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1876 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1878 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1880 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1882 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1884 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1886 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1887 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1888 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1889 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1890 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1891 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1892 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1893 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1894 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1899 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1901 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1965 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1968 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1976 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
2021 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
2025 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2095 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2107 ret = ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2136 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2139 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2142 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2145 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2148 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2153 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2155 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2157 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2160 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2163 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2166 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2171 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2173 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2175 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2178 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2181 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2184 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2189 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2191 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2221 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2224 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2227 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2230 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2232 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2245 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2247 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2250 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2253 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2255 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2267 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2270 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2273 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2276 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2278 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2310 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2313 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2316 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2415 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2419 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2420 &tmp, pi->sram_end); in ci_init_arb_table_index()
2427 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2428 tmp, pi->sram_end); in ci_init_arb_table_index()
2548 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2555 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2556 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2558 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2559 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2568 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2571 pi->sram_end); in ci_do_program_memory_timing_parameters()
2578 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2580 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2590 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2596 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2604 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2629 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2630 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2643 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2644 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2794 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2795 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2796 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2797 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2798 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2799 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2800 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2801 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2802 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2803 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2821 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2827 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2879 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2909 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2919 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2929 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2930 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2931 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2936 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2937 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2940 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2943 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2944 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2947 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2948 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2958 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2992 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2995 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2996 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2997 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2998 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
3003 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
3004 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3006 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3008 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3030 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3031 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3032 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3033 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3052 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3053 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3055 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3058 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3075 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3077 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3079 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3081 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3083 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3084 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3085 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3093 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3107 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3108 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3125 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3132 pi->ulv.supported = false; in ci_populate_ulv_level()
3136 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3150 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3163 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3165 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3166 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3167 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3168 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3187 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3220 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3238 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3254 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3278 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3279 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3280 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3284 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3292 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3293 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3297 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3299 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3302 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3304 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3305 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3310 pi->sram_end); in ci_populate_all_graphic_levels()
3325 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3326 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3327 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3331 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3341 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3346 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3350 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3351 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3352 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3353 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3356 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3358 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3359 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3362 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3367 pi->sram_end); in ci_populate_all_memory_levels()
3395 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3397 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3400 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3401 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3402 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3403 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3404 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3405 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3409 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3413 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3414 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3415 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3417 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3418 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3419 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3420 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3421 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3422 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3423 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3424 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3425 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3426 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3427 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3428 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3429 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3430 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3431 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3432 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3433 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3434 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3436 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3443 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3461 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3464 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3467 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3470 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3473 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3476 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3479 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3482 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3484 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3486 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3488 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3492 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3495 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3497 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3499 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3501 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3506 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3508 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3510 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3512 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3517 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3519 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3521 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3527 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3529 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3531 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3557 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3558 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3560 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3567 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3578 if (pi->mem_gddr5) in ci_init_smc_table()
3582 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3629 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3630 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3631 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3633 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3634 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3635 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3637 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3638 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3639 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3656 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3658 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3666 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3668 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3692 pi->dpm_table_start + in ci_init_smc_table()
3696 pi->sram_end); in ci_init_smc_table()
3722 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3723 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3753 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3765 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3770 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3817 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3822 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3823 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3826 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3832 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3833 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3836 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3842 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3843 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3846 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3858 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3860 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3862 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3866 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3874 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3881 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3890 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3894 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3900 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3904 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3907 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3910 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3913 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3916 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3922 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3933 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3943 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3947 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3949 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3956 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3958 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3959 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3960 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3963 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3966 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3967 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3968 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3971 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3982 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3992 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3995 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3997 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
4004 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
4015 struct ci_power_info *pi = ci_get_pi(rdev);
4025 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4028 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4030 if (!pi->caps_samu_dpm)
4037 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4046 struct ci_power_info *pi = ci_get_pi(rdev);
4056 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4059 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4061 if (!pi->caps_acp_dpm)
4068 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4079 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4083 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4085 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4087 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4092 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4118 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4127 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4130 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4152 struct ci_power_info *pi = ci_get_pi(rdev);
4156 pi->smc_state_table.AcpBootLevel = 0;
4160 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4171 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4178 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4179 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4180 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4181 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4182 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4183 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4184 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4185 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4186 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4188 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4189 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4209 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4214 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4215 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4217 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4233 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4234 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4236 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4252 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4253 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4255 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4272 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4273 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4275 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4287 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4288 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4290 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4302 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4303 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4305 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4318 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4339 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4365 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4372 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4626 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4628 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4686 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4689 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4690 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4693 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4694 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4722 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4725 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4726 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4730 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4733 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4734 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4735 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4741 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4744 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4746 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4752 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4755 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4757 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4760 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4763 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4764 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4766 pi->sram_end); in ci_populate_initial_mc_reg_table()
4771 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4773 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4776 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4778 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4781 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4783 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4785 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4786 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4853 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4858 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4861 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4863 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4864 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4871 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4881 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4886 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4894 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4899 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4919 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4940 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4941 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4944 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4945 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4962 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4963 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4976 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4977 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5095 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5102 pi->mem_gddr5 = true; in ci_get_memory_type()
5104 pi->mem_gddr5 = false; in ci_get_memory_type()
5112 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5114 pi->current_rps = *rps; in ci_update_current_ps()
5115 pi->current_ps = *new_ps; in ci_update_current_ps()
5116 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5123 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5125 pi->requested_rps = *rps; in ci_update_requested_ps()
5126 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5127 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5132 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5138 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5145 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5146 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5167 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5173 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5181 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5184 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5186 if (pi->dynamic_ss) in ci_dpm_enable()
5188 if (pi->thermal_protection) in ci_dpm_enable()
5218 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5322 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5332 if (pi->thermal_protection) in ci_dpm_disable()
5353 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5354 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5355 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5359 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5388 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5410 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5478 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5490 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5491 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5494 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5498 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5502 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5503 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5504 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5509 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5510 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5511 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5512 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5517 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5518 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5519 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5520 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5521 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5522 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5523 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5524 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5525 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5528 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5529 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5530 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5531 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5532 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5533 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5534 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5535 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5536 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5682 struct ci_power_info *pi; in ci_dpm_init() local
5687 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5688 if (pi == NULL) in ci_dpm_init()
5690 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5695 pi->sys_pcie_mask = 0; in ci_dpm_init()
5698 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5702 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5705 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in ci_dpm_init()
5707 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5709 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5710 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5711 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5712 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5714 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5715 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5716 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5717 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5719 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5743 pi->dll_default_on = false; in ci_dpm_init()
5744 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5746 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5747 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5748 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5749 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5750 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5751 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5752 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5753 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5755 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5757 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5758 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5759 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5760 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5765 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5768 pi->caps_sclk_ds = true; in ci_dpm_init()
5770 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5771 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5772 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5773 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5777 pi->caps_fps = false; in ci_dpm_init()
5779 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5781 pi->caps_uvd_dpm = true; in ci_dpm_init()
5782 pi->caps_vce_dpm = true; in ci_dpm_init()
5816 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5817 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5818 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5820 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5821 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5822 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5825 pi->uvd_enabled = false; in ci_dpm_init()
5827 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5876 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5877 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5878 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5880 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5882 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5886 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5888 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5895 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5897 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5902 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5905 pi->pcie_performance_request = in ci_dpm_init()
5908 pi->pcie_performance_request = false; in ci_dpm_init()
5913 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5914 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5915 pi->dynamic_ss = true; in ci_dpm_init()
5917 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5918 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5919 pi->dynamic_ss = true; in ci_dpm_init()
5923 pi->thermal_protection = true; in ci_dpm_init()
5925 pi->thermal_protection = false; in ci_dpm_init()
5927 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5929 pi->uvd_power_gated = false; in ci_dpm_init()
5937 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5945 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5946 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5950 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5990 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5991 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
6001 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
6002 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()