831 			if (ps->performance_levels[i].mclk > max_limits->mclk)  in ci_apply_state_adjust_rules()
832 				ps->performance_levels[i].mclk = max_limits->mclk;  in ci_apply_state_adjust_rules()
833 			if (ps->performance_levels[i].sclk > max_limits->sclk)  in ci_apply_state_adjust_rules()
834 				ps->performance_levels[i].sclk = max_limits->sclk;  in ci_apply_state_adjust_rules()
841 		mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;  in ci_apply_state_adjust_rules()
842 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
844 		mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
845 		sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
855 	ps->performance_levels[0].sclk = sclk;  in ci_apply_state_adjust_rules()
856 	ps->performance_levels[0].mclk = mclk;  in ci_apply_state_adjust_rules()
858 	if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)  in ci_apply_state_adjust_rules()
859 		ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;  in ci_apply_state_adjust_rules()
862 		if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)  in ci_apply_state_adjust_rules()
863 			ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;  in ci_apply_state_adjust_rules()
865 		if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)  in ci_apply_state_adjust_rules()
866 			ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;  in ci_apply_state_adjust_rules()
2595 		    boot_state->performance_levels[0].sclk) {  in ci_populate_smc_initial_state()
2603 		    boot_state->performance_levels[0].mclk) {  in ci_populate_smc_initial_state()
3766 				  state->performance_levels[0].sclk,  in ci_trim_dpm_states()
3767 				  state->performance_levels[high_limit_count].sclk);  in ci_trim_dpm_states()
3771 				  state->performance_levels[0].mclk,  in ci_trim_dpm_states()
3772 				  state->performance_levels[high_limit_count].mclk);  in ci_trim_dpm_states()
3775 				state->performance_levels[0].pcie_gen,  in ci_trim_dpm_states()
3776 				state->performance_levels[0].pcie_lane,  in ci_trim_dpm_states()
3777 				state->performance_levels[high_limit_count].pcie_gen,  in ci_trim_dpm_states()
3778 				state->performance_levels[high_limit_count].pcie_lane);  in ci_trim_dpm_states()
3861 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3863 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_find_dpm_states_clocks_in_dpm_table()
3902 	u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
3903 	u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;  in ci_populate_and_upload_sclk_mclk_dpm_levels()
4805 		pcie_speed = state->performance_levels[i].pcie_gen;  in ci_get_maximum_link_speed()
5480 	struct ci_pl *pl = &ps->performance_levels[index];  in ci_parse_pplib_clock_info()
5967 		pl = &ps->performance_levels[i];  in ci_dpm_print_power_state()
5994 		return requested_state->performance_levels[0].sclk;  in ci_dpm_get_sclk()
5996 		return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;  in ci_dpm_get_sclk()
6005 		return requested_state->performance_levels[0].mclk;  in ci_dpm_get_mclk()
6007 		return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;  in ci_dpm_get_mclk()