2877 					   SMU7_Discrete_MemoryLevel *memory_level)  in ci_populate_single_memory_level()  argument
2886 						    memory_clock, &memory_level->MinVddc);  in ci_populate_single_memory_level()
2894 						    memory_clock, &memory_level->MinVddci);  in ci_populate_single_memory_level()
2902 						    memory_clock, &memory_level->MinMvdd);  in ci_populate_single_memory_level()
2907 	memory_level->MinVddcPhases = 1;  in ci_populate_single_memory_level()
2913 						      &memory_level->MinVddcPhases);  in ci_populate_single_memory_level()
2915 	memory_level->EnabledForThrottle = 1;  in ci_populate_single_memory_level()
2916 	memory_level->UpH = 0;  in ci_populate_single_memory_level()
2917 	memory_level->DownH = 100;  in ci_populate_single_memory_level()
2918 	memory_level->VoltageDownH = 0;  in ci_populate_single_memory_level()
2919 	memory_level->ActivityLevel = (u16)pi->mclk_activity_target;  in ci_populate_single_memory_level()
2921 	memory_level->StutterEnable = false;  in ci_populate_single_memory_level()
2922 	memory_level->StrobeEnable = false;  in ci_populate_single_memory_level()
2923 	memory_level->EdcReadEnable = false;  in ci_populate_single_memory_level()
2924 	memory_level->EdcWriteEnable = false;  in ci_populate_single_memory_level()
2925 	memory_level->RttEnable = false;  in ci_populate_single_memory_level()
2927 	memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;  in ci_populate_single_memory_level()
2934 		memory_level->StutterEnable = true;  in ci_populate_single_memory_level()
2938 		memory_level->StrobeEnable = 1;  in ci_populate_single_memory_level()
2941 		memory_level->StrobeRatio =  in ci_populate_single_memory_level()
2942 			si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);  in ci_populate_single_memory_level()
2945 			memory_level->EdcReadEnable = true;  in ci_populate_single_memory_level()
2949 			memory_level->EdcWriteEnable = true;  in ci_populate_single_memory_level()
2951 		if (memory_level->StrobeEnable) {  in ci_populate_single_memory_level()
2961 		memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);  in ci_populate_single_memory_level()
2965 …ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_s…  in ci_populate_single_memory_level()
2969 	memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);  in ci_populate_single_memory_level()
2970 	memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);  in ci_populate_single_memory_level()
2971 	memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);  in ci_populate_single_memory_level()
2972 	memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);  in ci_populate_single_memory_level()
2974 	memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);  in ci_populate_single_memory_level()
2975 	memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);  in ci_populate_single_memory_level()
2976 	memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);  in ci_populate_single_memory_level()
2977 	memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);  in ci_populate_single_memory_level()
2978 	memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);  in ci_populate_single_memory_level()
2979 	memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);  in ci_populate_single_memory_level()
2980 	memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);  in ci_populate_single_memory_level()
2981 	memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);  in ci_populate_single_memory_level()
2982 	memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);  in ci_populate_single_memory_level()
2983 	memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);  in ci_populate_single_memory_level()
2984 	memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);  in ci_populate_single_memory_level()