Lines Matching refs:dpm
198 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi()
283 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL) in ci_populate_bapm_vddc_vid_sidd()
285 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8) in ci_populate_bapm_vddc_vid_sidd()
287 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count != in ci_populate_bapm_vddc_vid_sidd()
288 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count) in ci_populate_bapm_vddc_vid_sidd()
291 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) { in ci_populate_bapm_vddc_vid_sidd()
292 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_populate_bapm_vddc_vid_sidd()
293 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1); in ci_populate_bapm_vddc_vid_sidd()
294 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2); in ci_populate_bapm_vddc_vid_sidd()
295 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3); in ci_populate_bapm_vddc_vid_sidd()
297 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc); in ci_populate_bapm_vddc_vid_sidd()
298 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage); in ci_populate_bapm_vddc_vid_sidd()
338 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256; in ci_populate_tdc_limit()
371 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) || in ci_populate_fuzzy_fan()
372 (rdev->pm.dpm.fan.fan_output_sensitivity == 0)) in ci_populate_fuzzy_fan()
373 rdev->pm.dpm.fan.fan_output_sensitivity = in ci_populate_fuzzy_fan()
374 rdev->pm.dpm.fan.default_fan_output_sensitivity; in ci_populate_fuzzy_fan()
377 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity); in ci_populate_fuzzy_fan()
420 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_vddc_base_leakage_sidd()
437 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_populate_bapm_parameters_in_dpm_table()
438 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; in ci_populate_bapm_parameters_in_dpm_table()
672 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_enable_power_containment()
746 rdev->pm.dpm.dyn_state.cac_tdp_table; in ci_power_control_set_level()
754 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment); in ci_power_control_set_level()
806 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; in ci_apply_state_adjust_rules()
807 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; in ci_apply_state_adjust_rules()
813 if ((rdev->pm.dpm.new_active_crtc_count > 1) || in ci_apply_state_adjust_rules()
824 if (rdev->pm.dpm.ac_power) in ci_apply_state_adjust_rules()
825 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_apply_state_adjust_rules()
827 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_apply_state_adjust_rules()
829 if (rdev->pm.dpm.ac_power == false) { in ci_apply_state_adjust_rules()
849 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) in ci_apply_state_adjust_rules()
850 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; in ci_apply_state_adjust_rules()
851 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) in ci_apply_state_adjust_rules()
852 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; in ci_apply_state_adjust_rules()
900 rdev->pm.dpm.thermal.min_temp = low_temp; in ci_thermal_set_temperature_range()
901 rdev->pm.dpm.thermal.max_temp = high_temp; in ci_thermal_set_temperature_range()
969 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
976 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
980 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; in ci_thermal_setup_fan_table()
984 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; in ci_thermal_setup_fan_table()
985 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; in ci_thermal_setup_fan_table()
987 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; in ci_thermal_setup_fan_table()
988 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; in ci_thermal_setup_fan_table()
993 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); in ci_thermal_setup_fan_table()
994 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); in ci_thermal_setup_fan_table()
995 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); in ci_thermal_setup_fan_table()
1002 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); in ci_thermal_setup_fan_table()
1012 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * in ci_thermal_setup_fan_table()
1028 rdev->pm.dpm.fan.ucode_fan_control = false; in ci_thermal_setup_fan_table()
1047 rdev->pm.dpm.fan.default_max_fan_pwm); in ci_fan_ctrl_start_smc_fan_control()
1137 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1142 if (rdev->pm.dpm.fan.ucode_fan_control) in ci_fan_ctrl_set_mode()
1199 if (rdev->pm.dpm.fan.ucode_fan_control)
1232 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_smc_fan_control()
1264 if (rdev->pm.dpm.fan.ucode_fan_control) { in ci_thermal_start_thermal_controller()
1348 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) { in ci_get_leakage_voltages()
1450 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) in ci_enable_vr_hot_gpio_interrupt()
1636 rdev->pm.dpm.dyn_state.cac_tdp_table;
1995 if (rdev->pm.dpm.new_active_crtc_count > 0) in ci_program_display_gap()
2015 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1)); in ci_program_display_gap()
2147 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_construct_voltage_tables()
2165 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_construct_voltage_tables()
2183 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_construct_voltage_tables()
2314 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) { in ci_populate_mvdd_value()
2315 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) { in ci_populate_mvdd_value()
2321 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count) in ci_populate_mvdd_value()
2337 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) in ci_get_std_voltage_value_sidd()
2340 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { in ci_get_std_voltage_value_sidd()
2341 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2343 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2345 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2348 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2350 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2352 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2358 …for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { in ci_get_std_voltage_value_sidd()
2360 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { in ci_get_std_voltage_value_sidd()
2362 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) in ci_get_std_voltage_value_sidd()
2365 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1; in ci_get_std_voltage_value_sidd()
2367 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2369 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE; in ci_get_std_voltage_value_sidd()
2593 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) { in ci_populate_smc_initial_state()
2594 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >= in ci_populate_smc_initial_state()
2601 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) { in ci_populate_smc_initial_state()
2602 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >= in ci_populate_smc_initial_state()
2656 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count; in ci_populate_smc_uvd_level()
2660 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk; in ci_populate_smc_uvd_level()
2662 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk; in ci_populate_smc_uvd_level()
2664 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_uvd_level()
2699 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count; in ci_populate_smc_vce_level()
2703 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk; in ci_populate_smc_vce_level()
2705 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_vce_level()
2732 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count); in ci_populate_smc_acp_level()
2736 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_acp_level()
2738 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v; in ci_populate_smc_acp_level()
2764 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count; in ci_populate_smc_samu_level()
2768 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk; in ci_populate_smc_samu_level()
2770 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE; in ci_populate_smc_samu_level()
2883 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2885 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, in ci_populate_single_memory_level()
2891 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2893 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, in ci_populate_single_memory_level()
2899 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) { in ci_populate_single_memory_level()
2901 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk, in ci_populate_single_memory_level()
2911 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_memory_level()
2933 (rdev->pm.dpm.new_active_crtc_count <= 2)) in ci_populate_single_memory_level()
3126 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time; in ci_populate_ulv_level()
3137 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3141 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage; in ci_populate_ulv_level()
3143 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v) in ci_populate_ulv_level()
3147 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) * in ci_populate_ulv_level()
3228 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, in ci_populate_single_graphic_level()
3240 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, in ci_populate_single_graphic_level()
3445 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_setup_default_dpm_tables()
3447 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_setup_default_dpm_tables()
3449 &rdev->pm.dpm.dyn_state.cac_leakage_table; in ci_setup_default_dpm_tables()
3514 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_setup_default_dpm_tables()
3524 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk; in ci_setup_default_dpm_tables()
3559 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; in ci_init_smc_table()
3572 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) in ci_init_smc_table()
3575 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) in ci_init_smc_table()
3786 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk; in ci_apply_disp_minimum_voltage_request()
3788 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_apply_disp_minimum_voltage_request()
3892 if (rdev->pm.dpm.current_active_crtc_count != in ci_find_dpm_states_clocks_in_dpm_table()
3893 rdev->pm.dpm.new_active_crtc_count) in ci_find_dpm_states_clocks_in_dpm_table()
3937 if (rdev->pm.dpm.ac_power) in ci_enable_uvd_dpm()
3938 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_uvd_dpm()
3940 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_uvd_dpm()
3945 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_uvd_dpm()
3946 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_uvd_dpm()
3986 if (rdev->pm.dpm.ac_power) in ci_enable_vce_dpm()
3987 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_enable_vce_dpm()
3989 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; in ci_enable_vce_dpm()
3993 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) { in ci_enable_vce_dpm()
3994 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) { in ci_enable_vce_dpm()
4019 if (rdev->pm.dpm.ac_power)
4020 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4022 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4026 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4027 … if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4050 if (rdev->pm.dpm.ac_power)
4051 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4053 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
4057 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
4058 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
4084 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0)) in ci_update_uvd_dpm()
4088 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; in ci_update_uvd_dpm()
4104 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; in ci_get_vce_boot_level()
4331 rdev->pm.dpm.forced_level = level; in ci_dpm_force_performance_level()
4921 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk; in ci_set_private_data_variables_based_on_pptable()
4923 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4925 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk; in ci_set_private_data_variables_based_on_pptable()
4948 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = in ci_set_private_data_variables_based_on_pptable()
4950 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = in ci_set_private_data_variables_based_on_pptable()
4952 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = in ci_set_private_data_variables_based_on_pptable()
4954 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = in ci_set_private_data_variables_based_on_pptable()
5067 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); in ci_patch_dependency_tables_with_leakage()
5069 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5071 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk); in ci_patch_dependency_tables_with_leakage()
5073 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); in ci_patch_dependency_tables_with_leakage()
5075 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5077 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5079 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5081 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table); in ci_patch_dependency_tables_with_leakage()
5083 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table); in ci_patch_dependency_tables_with_leakage()
5085 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac); in ci_patch_dependency_tables_with_leakage()
5087 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc); in ci_patch_dependency_tables_with_leakage()
5089 &rdev->pm.dpm.dyn_state.cac_leakage_table); in ci_patch_dependency_tables_with_leakage()
5133 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; in ci_dpm_pre_set_power_state()
5168 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_enable()
5323 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; in ci_dpm_disable()
5469 rdev->pm.dpm.boot_ps = rps; in ci_parse_pplib_non_clock_info()
5471 rdev->pm.dpm.uvd_ps = rps; in ci_parse_pplib_non_clock_info()
5575 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, in ci_parse_power_table()
5578 if (!rdev->pm.dpm.ps) in ci_parse_power_table()
5591 kfree(rdev->pm.dpm.ps); in ci_parse_power_table()
5594 rdev->pm.dpm.ps[i].ps_priv = ps; in ci_parse_power_table()
5595 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], in ci_parse_power_table()
5610 &rdev->pm.dpm.ps[i], k, in ci_parse_power_table()
5616 rdev->pm.dpm.num_ps = state_array->ucNumEntries; in ci_parse_power_table()
5621 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; in ci_parse_power_table()
5628 rdev->pm.dpm.vce_states[i].sclk = sclk; in ci_parse_power_table()
5629 rdev->pm.dpm.vce_states[i].mclk = mclk; in ci_parse_power_table()
5666 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { in ci_dpm_fini()
5667 kfree(rdev->pm.dpm.ps[i].ps_priv); in ci_dpm_fini()
5669 kfree(rdev->pm.dpm.ps); in ci_dpm_fini()
5670 kfree(rdev->pm.dpm.priv); in ci_dpm_fini()
5671 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); in ci_dpm_fini()
5690 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5788 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = in ci_dpm_init()
5792 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { in ci_dpm_init()
5796 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; in ci_dpm_init()
5797 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; in ci_dpm_init()
5798 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; in ci_dpm_init()
5799 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; in ci_dpm_init()
5800 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; in ci_dpm_init()
5801 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; in ci_dpm_init()
5802 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; in ci_dpm_init()
5803 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; in ci_dpm_init()
5804 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; in ci_dpm_init()
5806 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; in ci_dpm_init()
5807 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; in ci_dpm_init()
5808 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; in ci_dpm_init()
5810 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; in ci_dpm_init()
5811 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; in ci_dpm_init()
5812 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; in ci_dpm_init()
5813 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; in ci_dpm_init()
5832 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5835 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT; in ci_dpm_init()
5841 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5844 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC; in ci_dpm_init()
5884 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) { in ci_dpm_init()
5890 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL; in ci_dpm_init()
5893 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) { in ci_dpm_init()
5899 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL; in ci_dpm_init()
5932 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || in ci_dpm_init()
5933 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in ci_dpm_init()
5934 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = in ci_dpm_init()
5935 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; in ci_dpm_init()