Lines Matching refs:dpcd
306 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
312 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
313 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
374 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) in radeon_dp_probe_oui()
395 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
397 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd), in radeon_dp_getdpcd()
398 dig_connector->dpcd); in radeon_dp_getdpcd()
405 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
465 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_set_link_config()
492 ret = radeon_dp_get_dp_link_config(connector, dig_connector->dpcd, in radeon_dp_mode_valid_helper()
531 if (dig_connector->dpcd[0] >= 0x11) { in radeon_dp_set_rx_power_state()
547 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
612 if (dp_info->dpcd[3] & 0x1) in radeon_dp_link_train_init()
624 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in radeon_dp_link_train_init()
685 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); in radeon_dp_link_train_cr()
748 drm_dp_link_train_channel_eq_delay(dp_info->dpcd); in radeon_dp_link_train_ce()
844 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); in radeon_dp_link_train()