1157 	u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);  in dce4_crtc_do_set_base()  local
1206 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1214 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1222 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1229 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);  in dce4_crtc_do_set_base()
1237 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1245 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1255 		fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1264 		fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) |  in dce4_crtc_do_set_base()
1267 		fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);  in dce4_crtc_do_set_base()
1405 	WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in dce4_crtc_do_set_base()
1478 	u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;  in avivo_crtc_do_set_base()  local
1528 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1536 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1544 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;  in avivo_crtc_do_set_base()
1553 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1562 		fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1573 			fb_swap =  in avivo_crtc_do_set_base()
1579 		fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT;  in avivo_crtc_do_set_base()
1626 		WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);  in avivo_crtc_do_set_base()