54 	dispc_write_reg(dispc, idx, \
358 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val)  in dispc_write_reg()  function
429 	dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
765 	dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value);  in dispc_ovl_write_firh_reg()
772 	dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value);  in dispc_ovl_write_firhv_reg()
779 	dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value);  in dispc_ovl_write_firv_reg()
788 	dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value);  in dispc_ovl_write_firh2_reg()
797 	dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value);  in dispc_ovl_write_firhv2_reg()
806 	dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value);  in dispc_ovl_write_firv2_reg()
877 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));  in dispc_ovl_write_color_conv_coef()
878 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy,  ct->rcb));  in dispc_ovl_write_color_conv_coef()
879 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));  in dispc_ovl_write_color_conv_coef()
880 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));  in dispc_ovl_write_color_conv_coef()
881 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));  in dispc_ovl_write_color_conv_coef()
895 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg,  ct->yr));  in dispc_wb_write_color_conv_coef()
896 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb));  in dispc_wb_write_color_conv_coef()
897 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg));  in dispc_wb_write_color_conv_coef()
898 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr));  in dispc_wb_write_color_conv_coef()
899 	dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb));  in dispc_wb_write_color_conv_coef()
937 	dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr);  in dispc_ovl_set_ba0()
943 	dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr);  in dispc_ovl_set_ba1()
949 	dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr);  in dispc_ovl_set_ba0_uv()
955 	dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr);  in dispc_ovl_set_ba1_uv()
969 	dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val);  in dispc_ovl_set_pos()
979 		dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);  in dispc_ovl_set_input_size()
981 		dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);  in dispc_ovl_set_input_size()
995 		dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);  in dispc_ovl_set_output_size()
997 		dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);  in dispc_ovl_set_output_size()
1050 	dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc);  in dispc_ovl_set_pix_inc()
1056 	dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc);  in dispc_ovl_set_row_inc()
1205 	dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);  in dispc_ovl_set_channel_out()
1327 	dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r);  in dispc_mgr_set_cpr_coef()
1328 	dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g);  in dispc_mgr_set_cpr_coef()
1329 	dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b);  in dispc_mgr_set_cpr_coef()
1341 	dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);  in dispc_ovl_set_vid_color_conv()
1367 	dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val);  in dispc_mgr_set_size()
1412 		dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v);  in dispc_init_fifos()
1487 	dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),  in dispc_ovl_set_fifo_threshold()
1498 		dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane),  in dispc_ovl_set_fifo_threshold()
1577 	dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane),  in dispc_ovl_set_mflag_threshold()
1595 	dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE,  in dispc_init_mflag()
1655 		dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val);  in dispc_ovl_set_fir()
1658 		dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val);  in dispc_ovl_set_fir()
1677 	dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val);  in dispc_ovl_set_vid_accu0()
1695 	dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val);  in dispc_ovl_set_vid_accu1()
1705 	dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val);  in dispc_ovl_set_vid_accu2_0()
1715 	dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val);  in dispc_ovl_set_vid_accu2_1()
1860 	dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);  in dispc_ovl_set_scaling_common()
2846 	dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);  in dispc_wb_setup()
2936 	dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color);  in dispc_mgr_set_default_color()
2946 	dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key);  in dispc_mgr_set_trans_key()
3038 	dispc_write_reg(dispc, DISPC_CONTROL, l);  in dispc_mgr_set_io_pad_mode()
3135 	dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h);  in _dispc_mgr_set_lcd_timings()
3136 	dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v);  in _dispc_mgr_set_lcd_timings()
3177 	dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l);  in _dispc_mgr_set_lcd_timings()
3266 	dispc_write_reg(dispc, DISPC_DIVISORo(channel),  in dispc_mgr_set_lcd_divisor()
3761 	dispc_write_reg(dispc, DISPC_IRQSTATUS, mask);  in dispc_clear_irqstatus()
3771 	dispc_write_reg(dispc, DISPC_IRQENABLE, mask);  in dispc_write_irqenable()
3816 		dispc_write_reg(dispc, gdesc->reg, v);  in dispc_mgr_write_gamma_table()
3932 		dispc_write_reg(dispc, DISPC_DIVISOR, l);  in _omap_dispc_initial_config()