Lines Matching refs:dispc
50 #define REG_GET(dispc, idx, start, end) \ argument
51 FLD_GET(dispc_read_reg(dispc, idx), start, end)
53 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
54 dispc_write_reg(dispc, idx, \
55 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
100 int (*calc_scaling)(struct dispc_device *dispc,
344 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
345 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
346 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
348 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
351 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
353 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
356 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
358 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) in dispc_write_reg() argument
360 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
363 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) in dispc_read_reg() argument
365 return __raw_readl(dispc->base + idx); in dispc_read_reg()
368 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_read() argument
373 return REG_GET(dispc, rfld.reg, rfld.high, rfld.low); in mgr_fld_read()
376 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_write() argument
384 spin_lock_irqsave(&dispc->control_lock, flags); in mgr_fld_write()
385 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
386 spin_unlock_irqrestore(&dispc->control_lock, flags); in mgr_fld_write()
388 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
392 static int dispc_get_num_ovls(struct dispc_device *dispc) in dispc_get_num_ovls() argument
394 return dispc->feat->num_ovls; in dispc_get_num_ovls()
397 static int dispc_get_num_mgrs(struct dispc_device *dispc) in dispc_get_num_mgrs() argument
399 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
402 static void dispc_get_reg_field(struct dispc_device *dispc, in dispc_get_reg_field() argument
406 if (id >= dispc->feat->num_reg_fields) in dispc_get_reg_field()
409 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
410 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
413 static bool dispc_has_feature(struct dispc_device *dispc, in dispc_has_feature() argument
418 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
419 if (dispc->feat->features[i] == id) in dispc_has_feature()
426 #define SR(dispc, reg) \ argument
427 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
428 #define RR(dispc, reg) \ argument
429 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
431 static void dispc_save_context(struct dispc_device *dispc) in dispc_save_context() argument
437 SR(dispc, IRQENABLE); in dispc_save_context()
438 SR(dispc, CONTROL); in dispc_save_context()
439 SR(dispc, CONFIG); in dispc_save_context()
440 SR(dispc, LINE_NUMBER); in dispc_save_context()
441 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_save_context()
442 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_save_context()
443 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
444 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_save_context()
445 SR(dispc, CONTROL2); in dispc_save_context()
446 SR(dispc, CONFIG2); in dispc_save_context()
448 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_save_context()
449 SR(dispc, CONTROL3); in dispc_save_context()
450 SR(dispc, CONFIG3); in dispc_save_context()
453 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_save_context()
454 SR(dispc, DEFAULT_COLOR(i)); in dispc_save_context()
455 SR(dispc, TRANS_COLOR(i)); in dispc_save_context()
456 SR(dispc, SIZE_MGR(i)); in dispc_save_context()
459 SR(dispc, TIMING_H(i)); in dispc_save_context()
460 SR(dispc, TIMING_V(i)); in dispc_save_context()
461 SR(dispc, POL_FREQ(i)); in dispc_save_context()
462 SR(dispc, DIVISORo(i)); in dispc_save_context()
464 SR(dispc, DATA_CYCLE1(i)); in dispc_save_context()
465 SR(dispc, DATA_CYCLE2(i)); in dispc_save_context()
466 SR(dispc, DATA_CYCLE3(i)); in dispc_save_context()
468 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_save_context()
469 SR(dispc, CPR_COEF_R(i)); in dispc_save_context()
470 SR(dispc, CPR_COEF_G(i)); in dispc_save_context()
471 SR(dispc, CPR_COEF_B(i)); in dispc_save_context()
475 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_save_context()
476 SR(dispc, OVL_BA0(i)); in dispc_save_context()
477 SR(dispc, OVL_BA1(i)); in dispc_save_context()
478 SR(dispc, OVL_POSITION(i)); in dispc_save_context()
479 SR(dispc, OVL_SIZE(i)); in dispc_save_context()
480 SR(dispc, OVL_ATTRIBUTES(i)); in dispc_save_context()
481 SR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_save_context()
482 SR(dispc, OVL_ROW_INC(i)); in dispc_save_context()
483 SR(dispc, OVL_PIXEL_INC(i)); in dispc_save_context()
484 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_save_context()
485 SR(dispc, OVL_PRELOAD(i)); in dispc_save_context()
487 SR(dispc, OVL_WINDOW_SKIP(i)); in dispc_save_context()
488 SR(dispc, OVL_TABLE_BA(i)); in dispc_save_context()
491 SR(dispc, OVL_FIR(i)); in dispc_save_context()
492 SR(dispc, OVL_PICTURE_SIZE(i)); in dispc_save_context()
493 SR(dispc, OVL_ACCU0(i)); in dispc_save_context()
494 SR(dispc, OVL_ACCU1(i)); in dispc_save_context()
497 SR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_save_context()
500 SR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_save_context()
503 SR(dispc, OVL_CONV_COEF(i, j)); in dispc_save_context()
505 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_save_context()
507 SR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_save_context()
510 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_save_context()
511 SR(dispc, OVL_BA0_UV(i)); in dispc_save_context()
512 SR(dispc, OVL_BA1_UV(i)); in dispc_save_context()
513 SR(dispc, OVL_FIR2(i)); in dispc_save_context()
514 SR(dispc, OVL_ACCU2_0(i)); in dispc_save_context()
515 SR(dispc, OVL_ACCU2_1(i)); in dispc_save_context()
518 SR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_save_context()
521 SR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_save_context()
524 SR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_save_context()
526 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_save_context()
527 SR(dispc, OVL_ATTRIBUTES2(i)); in dispc_save_context()
530 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_save_context()
531 SR(dispc, DIVISOR); in dispc_save_context()
533 dispc->ctx_valid = true; in dispc_save_context()
538 static void dispc_restore_context(struct dispc_device *dispc) in dispc_restore_context() argument
544 if (!dispc->ctx_valid) in dispc_restore_context()
549 RR(dispc, CONFIG); in dispc_restore_context()
550 RR(dispc, LINE_NUMBER); in dispc_restore_context()
551 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_restore_context()
552 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_restore_context()
553 RR(dispc, GLOBAL_ALPHA); in dispc_restore_context()
554 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
555 RR(dispc, CONFIG2); in dispc_restore_context()
556 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
557 RR(dispc, CONFIG3); in dispc_restore_context()
559 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_restore_context()
560 RR(dispc, DEFAULT_COLOR(i)); in dispc_restore_context()
561 RR(dispc, TRANS_COLOR(i)); in dispc_restore_context()
562 RR(dispc, SIZE_MGR(i)); in dispc_restore_context()
565 RR(dispc, TIMING_H(i)); in dispc_restore_context()
566 RR(dispc, TIMING_V(i)); in dispc_restore_context()
567 RR(dispc, POL_FREQ(i)); in dispc_restore_context()
568 RR(dispc, DIVISORo(i)); in dispc_restore_context()
570 RR(dispc, DATA_CYCLE1(i)); in dispc_restore_context()
571 RR(dispc, DATA_CYCLE2(i)); in dispc_restore_context()
572 RR(dispc, DATA_CYCLE3(i)); in dispc_restore_context()
574 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_restore_context()
575 RR(dispc, CPR_COEF_R(i)); in dispc_restore_context()
576 RR(dispc, CPR_COEF_G(i)); in dispc_restore_context()
577 RR(dispc, CPR_COEF_B(i)); in dispc_restore_context()
581 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_restore_context()
582 RR(dispc, OVL_BA0(i)); in dispc_restore_context()
583 RR(dispc, OVL_BA1(i)); in dispc_restore_context()
584 RR(dispc, OVL_POSITION(i)); in dispc_restore_context()
585 RR(dispc, OVL_SIZE(i)); in dispc_restore_context()
586 RR(dispc, OVL_ATTRIBUTES(i)); in dispc_restore_context()
587 RR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_restore_context()
588 RR(dispc, OVL_ROW_INC(i)); in dispc_restore_context()
589 RR(dispc, OVL_PIXEL_INC(i)); in dispc_restore_context()
590 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_restore_context()
591 RR(dispc, OVL_PRELOAD(i)); in dispc_restore_context()
593 RR(dispc, OVL_WINDOW_SKIP(i)); in dispc_restore_context()
594 RR(dispc, OVL_TABLE_BA(i)); in dispc_restore_context()
597 RR(dispc, OVL_FIR(i)); in dispc_restore_context()
598 RR(dispc, OVL_PICTURE_SIZE(i)); in dispc_restore_context()
599 RR(dispc, OVL_ACCU0(i)); in dispc_restore_context()
600 RR(dispc, OVL_ACCU1(i)); in dispc_restore_context()
603 RR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_restore_context()
606 RR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_restore_context()
609 RR(dispc, OVL_CONV_COEF(i, j)); in dispc_restore_context()
611 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_restore_context()
613 RR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_restore_context()
616 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_restore_context()
617 RR(dispc, OVL_BA0_UV(i)); in dispc_restore_context()
618 RR(dispc, OVL_BA1_UV(i)); in dispc_restore_context()
619 RR(dispc, OVL_FIR2(i)); in dispc_restore_context()
620 RR(dispc, OVL_ACCU2_0(i)); in dispc_restore_context()
621 RR(dispc, OVL_ACCU2_1(i)); in dispc_restore_context()
624 RR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_restore_context()
627 RR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_restore_context()
630 RR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_restore_context()
632 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_restore_context()
633 RR(dispc, OVL_ATTRIBUTES2(i)); in dispc_restore_context()
636 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_restore_context()
637 RR(dispc, DIVISOR); in dispc_restore_context()
640 RR(dispc, CONTROL); in dispc_restore_context()
641 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
642 RR(dispc, CONTROL2); in dispc_restore_context()
643 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
644 RR(dispc, CONTROL3); in dispc_restore_context()
646 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); in dispc_restore_context()
652 RR(dispc, IRQENABLE); in dispc_restore_context()
660 int dispc_runtime_get(struct dispc_device *dispc) in dispc_runtime_get() argument
666 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
671 void dispc_runtime_put(struct dispc_device *dispc) in dispc_runtime_put() argument
677 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
681 static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, in dispc_mgr_get_vsync_irq() argument
687 static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, in dispc_mgr_get_framedone_irq() argument
690 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
696 static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, in dispc_mgr_get_sync_lost_irq() argument
702 static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) in dispc_wb_get_framedone_irq() argument
707 static void dispc_mgr_enable(struct dispc_device *dispc, in dispc_mgr_enable() argument
710 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); in dispc_mgr_enable()
712 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_enable()
715 static bool dispc_mgr_is_enabled(struct dispc_device *dispc, in dispc_mgr_is_enabled() argument
718 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_is_enabled()
721 static bool dispc_mgr_go_busy(struct dispc_device *dispc, in dispc_mgr_go_busy() argument
724 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; in dispc_mgr_go_busy()
727 static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) in dispc_mgr_go() argument
729 WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); in dispc_mgr_go()
730 WARN_ON(dispc_mgr_go_busy(dispc, channel)); in dispc_mgr_go()
734 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); in dispc_mgr_go()
737 static bool dispc_wb_go_busy(struct dispc_device *dispc) in dispc_wb_go_busy() argument
739 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
742 static void dispc_wb_go(struct dispc_device *dispc) in dispc_wb_go() argument
747 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
752 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
758 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
761 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, in dispc_ovl_write_firh_reg() argument
765 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); in dispc_ovl_write_firh_reg()
768 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv_reg() argument
772 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); in dispc_ovl_write_firhv_reg()
775 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, in dispc_ovl_write_firv_reg() argument
779 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); in dispc_ovl_write_firv_reg()
782 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, in dispc_ovl_write_firh2_reg() argument
788 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); in dispc_ovl_write_firh2_reg()
791 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv2_reg() argument
797 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); in dispc_ovl_write_firhv2_reg()
800 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firv2_reg() argument
806 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); in dispc_ovl_write_firv2_reg()
809 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, in dispc_ovl_set_scale_coef() argument
821 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
839 dispc_ovl_write_firh_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
840 dispc_ovl_write_firhv_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
842 dispc_ovl_write_firh2_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
843 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
854 dispc_ovl_write_firv_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
856 dispc_ovl_write_firv2_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
871 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, in dispc_ovl_write_color_conv_coef() argument
877 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
878 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
879 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
880 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
881 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
883 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
888 static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc, in dispc_wb_write_color_conv_coef() argument
895 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr)); in dispc_wb_write_color_conv_coef()
896 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb)); in dispc_wb_write_color_conv_coef()
897 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg)); in dispc_wb_write_color_conv_coef()
898 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr)); in dispc_wb_write_color_conv_coef()
899 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb)); in dispc_wb_write_color_conv_coef()
901 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_wb_write_color_conv_coef()
906 static void dispc_setup_color_conv_coef(struct dispc_device *dispc) in dispc_setup_color_conv_coef() argument
909 int num_ovl = dispc_get_num_ovls(dispc); in dispc_setup_color_conv_coef()
928 dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim); in dispc_setup_color_conv_coef()
930 if (dispc->feat->has_writeback) in dispc_setup_color_conv_coef()
931 dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim); in dispc_setup_color_conv_coef()
934 static void dispc_ovl_set_ba0(struct dispc_device *dispc, in dispc_ovl_set_ba0() argument
937 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); in dispc_ovl_set_ba0()
940 static void dispc_ovl_set_ba1(struct dispc_device *dispc, in dispc_ovl_set_ba1() argument
943 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); in dispc_ovl_set_ba1()
946 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, in dispc_ovl_set_ba0_uv() argument
949 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); in dispc_ovl_set_ba0_uv()
952 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, in dispc_ovl_set_ba1_uv() argument
955 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); in dispc_ovl_set_ba1_uv()
958 static void dispc_ovl_set_pos(struct dispc_device *dispc, in dispc_ovl_set_pos() argument
969 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); in dispc_ovl_set_pos()
972 static void dispc_ovl_set_input_size(struct dispc_device *dispc, in dispc_ovl_set_input_size() argument
979 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_input_size()
981 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_input_size()
984 static void dispc_ovl_set_output_size(struct dispc_device *dispc, in dispc_ovl_set_output_size() argument
995 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_output_size()
997 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_output_size()
1000 static void dispc_ovl_set_zorder(struct dispc_device *dispc, in dispc_ovl_set_zorder() argument
1007 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
1010 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) in dispc_ovl_enable_zorder_planes() argument
1014 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_ovl_enable_zorder_planes()
1017 for (i = 0; i < dispc_get_num_ovls(dispc); i++) in dispc_ovl_enable_zorder_planes()
1018 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1021 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, in dispc_ovl_set_pre_mult_alpha() argument
1029 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
1032 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, in dispc_ovl_setup_global_alpha() argument
1044 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
1047 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, in dispc_ovl_set_pix_inc() argument
1050 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); in dispc_ovl_set_pix_inc()
1053 static void dispc_ovl_set_row_inc(struct dispc_device *dispc, in dispc_ovl_set_row_inc() argument
1056 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); in dispc_ovl_set_row_inc()
1059 static void dispc_ovl_set_color_mode(struct dispc_device *dispc, in dispc_ovl_set_color_mode() argument
1129 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
1132 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, in dispc_ovl_configure_burst_type() argument
1136 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) in dispc_ovl_configure_burst_type()
1140 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
1142 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); in dispc_ovl_configure_burst_type()
1145 static void dispc_ovl_set_channel_out(struct dispc_device *dispc, in dispc_ovl_set_channel_out() argument
1167 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_channel_out()
1168 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_ovl_set_channel_out()
1183 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_ovl_set_channel_out()
1205 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_channel_out()
1208 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, in dispc_ovl_get_channel_out() argument
1228 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_get_channel_out()
1233 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_ovl_get_channel_out()
1249 static void dispc_ovl_set_burst_size(struct dispc_device *dispc, in dispc_ovl_set_burst_size() argument
1257 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, in dispc_ovl_set_burst_size()
1261 static void dispc_configure_burst_sizes(struct dispc_device *dispc) in dispc_configure_burst_sizes() argument
1267 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_configure_burst_sizes()
1268 dispc_ovl_set_burst_size(dispc, i, burst_size); in dispc_configure_burst_sizes()
1269 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1270 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); in dispc_configure_burst_sizes()
1273 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, in dispc_ovl_get_burst_size() argument
1277 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1280 static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, in dispc_ovl_color_mode_supported() argument
1286 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1296 static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, in dispc_ovl_get_color_modes() argument
1299 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1302 static void dispc_mgr_enable_cpr(struct dispc_device *dispc, in dispc_mgr_enable_cpr() argument
1308 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); in dispc_mgr_enable_cpr()
1311 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, in dispc_mgr_set_cpr_coef() argument
1327 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); in dispc_mgr_set_cpr_coef()
1328 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); in dispc_mgr_set_cpr_coef()
1329 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); in dispc_mgr_set_cpr_coef()
1332 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, in dispc_ovl_set_vid_color_conv() argument
1339 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_vid_color_conv()
1341 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_vid_color_conv()
1344 static void dispc_ovl_enable_replication(struct dispc_device *dispc, in dispc_ovl_enable_replication() argument
1356 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); in dispc_ovl_enable_replication()
1359 static void dispc_mgr_set_size(struct dispc_device *dispc, in dispc_mgr_set_size() argument
1364 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1365 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1367 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); in dispc_mgr_set_size()
1370 static void dispc_init_fifos(struct dispc_device *dispc) in dispc_init_fifos() argument
1378 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1380 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); in dispc_init_fifos()
1382 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1383 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1386 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1392 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1402 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1405 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); in dispc_init_fifos()
1412 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); in dispc_init_fifos()
1414 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1415 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1421 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_fifos()
1426 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, in dispc_init_fifos()
1429 dispc_ovl_set_fifo_threshold(dispc, i, low, high); in dispc_init_fifos()
1432 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1437 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, in dispc_init_fifos()
1441 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_fifos()
1445 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, in dispc_ovl_get_fifo_size() argument
1451 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1452 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1453 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1459 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, in dispc_ovl_set_fifo_threshold() argument
1466 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1474 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1476 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1481 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1483 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1487 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1496 if (dispc_has_feature(dispc, FEAT_PRELOAD) && in dispc_ovl_set_fifo_threshold()
1497 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1498 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), in dispc_ovl_set_fifo_threshold()
1502 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) in dispc_enable_fifomerge() argument
1504 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { in dispc_enable_fifomerge()
1510 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); in dispc_enable_fifomerge()
1513 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, in dispc_ovl_compute_fifo_thresholds() argument
1522 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1526 burst_size = dispc_ovl_get_burst_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1527 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1531 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_ovl_compute_fifo_thresholds()
1532 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); in dispc_ovl_compute_fifo_thresholds()
1543 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { in dispc_ovl_compute_fifo_thresholds()
1560 static void dispc_ovl_set_mflag(struct dispc_device *dispc, in dispc_ovl_set_mflag() argument
1570 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); in dispc_ovl_set_mflag()
1573 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, in dispc_ovl_set_mflag_threshold() argument
1577 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), in dispc_ovl_set_mflag_threshold()
1581 static void dispc_init_mflag(struct dispc_device *dispc) in dispc_init_mflag() argument
1595 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, in dispc_init_mflag()
1599 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_mflag()
1600 u32 size = dispc_ovl_get_fifo_size(dispc, i); in dispc_init_mflag()
1601 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1604 dispc_ovl_set_mflag(dispc, i, true); in dispc_init_mflag()
1615 dispc_ovl_set_mflag_threshold(dispc, i, low, high); in dispc_init_mflag()
1618 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1619 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); in dispc_init_mflag()
1620 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1623 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); in dispc_init_mflag()
1634 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_mflag()
1638 static void dispc_ovl_set_fir(struct dispc_device *dispc, in dispc_ovl_set_fir() argument
1648 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, in dispc_ovl_set_fir()
1650 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, in dispc_ovl_set_fir()
1655 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); in dispc_ovl_set_fir()
1658 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); in dispc_ovl_set_fir()
1662 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu0() argument
1669 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu0()
1671 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu0()
1677 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); in dispc_ovl_set_vid_accu0()
1680 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu1() argument
1687 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu1()
1689 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu1()
1695 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); in dispc_ovl_set_vid_accu1()
1698 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_0() argument
1705 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); in dispc_ovl_set_vid_accu2_0()
1708 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_1() argument
1715 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); in dispc_ovl_set_vid_accu2_1()
1718 static void dispc_ovl_set_scale_param(struct dispc_device *dispc, in dispc_ovl_set_scale_param() argument
1730 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, in dispc_ovl_set_scale_param()
1732 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); in dispc_ovl_set_scale_param()
1735 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, in dispc_ovl_set_accu_uv() argument
1820 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); in dispc_ovl_set_accu_uv()
1821 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); in dispc_ovl_set_accu_uv()
1824 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, in dispc_ovl_set_scaling_common() argument
1836 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_common()
1839 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_scaling_common()
1848 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { in dispc_ovl_set_scaling_common()
1855 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { in dispc_ovl_set_scaling_common()
1860 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_ovl_set_scaling_common()
1875 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); in dispc_ovl_set_scaling_common()
1876 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); in dispc_ovl_set_scaling_common()
1879 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, in dispc_ovl_set_scaling_uv() argument
1894 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) in dispc_ovl_set_scaling_uv()
1900 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1905 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, in dispc_ovl_set_scaling_uv()
1948 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_uv()
1953 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1957 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); in dispc_ovl_set_scaling_uv()
1959 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); in dispc_ovl_set_scaling_uv()
1962 static void dispc_ovl_set_scaling(struct dispc_device *dispc, in dispc_ovl_set_scaling() argument
1972 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1976 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1981 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, in dispc_ovl_set_rotation_attrs() argument
2038 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); in dispc_ovl_set_rotation_attrs()
2039 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) in dispc_ovl_set_rotation_attrs()
2040 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2043 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { in dispc_ovl_set_rotation_attrs()
2050 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2288 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_24xx() argument
2302 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2309 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2312 *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_24xx()
2337 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_34xx() argument
2350 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2367 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2381 !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_34xx()
2425 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_44xx() argument
2439 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2440 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2445 in_width_max = dispc_core_clk_rate(dispc) in dispc_ovl_calc_scaling_44xx()
2484 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2492 static int dispc_ovl_calc_scaling(struct dispc_device *dispc, in dispc_ovl_calc_scaling() argument
2504 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2505 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2540 dispc_has_feature(dispc, FEAT_BURST_2D)) ? in dispc_ovl_calc_scaling()
2553 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2573 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2575 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { in dispc_ovl_calc_scaling()
2579 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2588 static int dispc_ovl_setup_common(struct dispc_device *dispc, in dispc_ovl_setup_common() argument
2613 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); in dispc_ovl_setup_common()
2614 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); in dispc_ovl_setup_common()
2649 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) in dispc_ovl_setup_common()
2652 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, in dispc_ovl_setup_common()
2714 dispc_ovl_set_color_mode(dispc, plane, fourcc); in dispc_ovl_setup_common()
2716 dispc_ovl_configure_burst_type(dispc, plane, rotation_type); in dispc_ovl_setup_common()
2718 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2721 dispc_ovl_set_ba0(dispc, plane, paddr + offset0); in dispc_ovl_setup_common()
2722 dispc_ovl_set_ba1(dispc, plane, paddr + offset1); in dispc_ovl_setup_common()
2725 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); in dispc_ovl_setup_common()
2726 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); in dispc_ovl_setup_common()
2729 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2732 dispc_ovl_set_row_inc(dispc, plane, row_inc); in dispc_ovl_setup_common()
2733 dispc_ovl_set_pix_inc(dispc, plane, pix_inc); in dispc_ovl_setup_common()
2738 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); in dispc_ovl_setup_common()
2740 dispc_ovl_set_input_size(dispc, plane, in_width, in_height); in dispc_ovl_setup_common()
2743 dispc_ovl_set_scaling(dispc, plane, in_width, in_height, in dispc_ovl_setup_common()
2746 dispc_ovl_set_output_size(dispc, plane, out_width, out_height); in dispc_ovl_setup_common()
2747 dispc_ovl_set_vid_color_conv(dispc, plane, cconv); in dispc_ovl_setup_common()
2750 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, in dispc_ovl_setup_common()
2753 dispc_ovl_set_zorder(dispc, plane, caps, zorder); in dispc_ovl_setup_common()
2754 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); in dispc_ovl_setup_common()
2755 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); in dispc_ovl_setup_common()
2757 dispc_ovl_enable_replication(dispc, plane, caps, replication); in dispc_ovl_setup_common()
2762 static int dispc_ovl_setup(struct dispc_device *dispc, in dispc_ovl_setup() argument
2769 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2778 dispc_ovl_set_channel_out(dispc, plane, channel); in dispc_ovl_setup()
2780 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2789 static int dispc_wb_setup(struct dispc_device *dispc, in dispc_wb_setup() argument
2813 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, in dispc_wb_setup()
2838 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_wb_setup()
2846 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_wb_setup()
2850 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); in dispc_wb_setup()
2866 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); in dispc_wb_setup()
2872 static bool dispc_has_writeback(struct dispc_device *dispc) in dispc_has_writeback() argument
2874 return dispc->feat->has_writeback; in dispc_has_writeback()
2877 static int dispc_ovl_enable(struct dispc_device *dispc, in dispc_ovl_enable() argument
2882 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); in dispc_ovl_enable()
2887 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, in dispc_lcd_enable_signal_polarity() argument
2890 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) in dispc_lcd_enable_signal_polarity()
2893 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); in dispc_lcd_enable_signal_polarity()
2896 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) in dispc_lcd_enable_signal() argument
2898 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) in dispc_lcd_enable_signal()
2901 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
2904 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) in dispc_pck_free_enable() argument
2906 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) in dispc_pck_free_enable()
2909 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); in dispc_pck_free_enable()
2912 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, in dispc_mgr_enable_fifohandcheck() argument
2916 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); in dispc_mgr_enable_fifohandcheck()
2920 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, in dispc_mgr_set_lcd_type_tft() argument
2923 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); in dispc_mgr_set_lcd_type_tft()
2926 static void dispc_set_loadmode(struct dispc_device *dispc, in dispc_set_loadmode() argument
2929 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
2933 static void dispc_mgr_set_default_color(struct dispc_device *dispc, in dispc_mgr_set_default_color() argument
2936 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); in dispc_mgr_set_default_color()
2939 static void dispc_mgr_set_trans_key(struct dispc_device *dispc, in dispc_mgr_set_trans_key() argument
2944 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); in dispc_mgr_set_trans_key()
2946 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); in dispc_mgr_set_trans_key()
2949 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, in dispc_mgr_enable_trans_key() argument
2952 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); in dispc_mgr_enable_trans_key()
2955 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, in dispc_mgr_enable_alpha_fixed_zorder() argument
2959 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) in dispc_mgr_enable_alpha_fixed_zorder()
2963 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); in dispc_mgr_enable_alpha_fixed_zorder()
2965 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); in dispc_mgr_enable_alpha_fixed_zorder()
2968 static void dispc_mgr_setup(struct dispc_device *dispc, in dispc_mgr_setup() argument
2972 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
2973 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
2975 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
2976 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, in dispc_mgr_setup()
2978 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_mgr_setup()
2979 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
2980 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
2984 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, in dispc_mgr_set_tft_data_lines() argument
3008 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); in dispc_mgr_set_tft_data_lines()
3011 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, in dispc_mgr_set_io_pad_mode() argument
3035 l = dispc_read_reg(dispc, DISPC_CONTROL); in dispc_mgr_set_io_pad_mode()
3038 dispc_write_reg(dispc, DISPC_CONTROL, l); in dispc_mgr_set_io_pad_mode()
3041 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, in dispc_mgr_enable_stallmode() argument
3044 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); in dispc_mgr_enable_stallmode()
3047 static void dispc_mgr_set_lcd_config(struct dispc_device *dispc, in dispc_mgr_set_lcd_config() argument
3051 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
3053 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
3054 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
3056 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
3058 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
3060 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
3062 dispc_mgr_set_lcd_type_tft(dispc, channel); in dispc_mgr_set_lcd_config()
3065 static bool _dispc_mgr_size_ok(struct dispc_device *dispc, in _dispc_mgr_size_ok() argument
3068 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
3069 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
3072 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, in _dispc_lcd_timings_ok() argument
3076 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3077 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3078 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3079 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3080 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
3081 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
3086 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, in _dispc_mgr_pclk_ok() argument
3091 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
3093 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3096 static int dispc_mgr_check_timings(struct dispc_device *dispc, in dispc_mgr_check_timings() argument
3100 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_check_timings()
3103 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_check_timings()
3111 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_check_timings()
3121 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, in _dispc_mgr_set_lcd_timings() argument
3128 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3129 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3130 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3131 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3132 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3133 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3135 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); in _dispc_mgr_set_lcd_timings()
3136 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); in _dispc_mgr_set_lcd_timings()
3174 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3177 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); in _dispc_mgr_set_lcd_timings()
3179 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3194 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3210 static void dispc_mgr_set_timings(struct dispc_device *dispc, in dispc_mgr_set_timings() argument
3220 if (dispc_mgr_check_timings(dispc, channel, &t)) { in dispc_mgr_set_timings()
3226 _dispc_mgr_set_lcd_timings(dispc, channel, &t); in dispc_mgr_set_timings()
3250 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3251 REG_FLD_MOD(dispc, DISPC_CONTROL, in dispc_mgr_set_timings()
3256 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); in dispc_mgr_set_timings()
3259 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_set_lcd_divisor() argument
3266 dispc_write_reg(dispc, DISPC_DIVISORo(channel), in dispc_mgr_set_lcd_divisor()
3269 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && in dispc_mgr_set_lcd_divisor()
3271 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3274 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_get_lcd_divisor() argument
3279 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_get_lcd_divisor()
3284 static unsigned long dispc_fclk_rate(struct dispc_device *dispc) in dispc_fclk_rate() argument
3289 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3292 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3297 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3306 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, in dispc_mgr_lclk_rate() argument
3315 return dispc_fclk_rate(dispc); in dispc_mgr_lclk_rate()
3317 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3320 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3325 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3331 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_lclk_rate()
3336 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, in dispc_mgr_pclk_rate() argument
3345 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_pclk_rate()
3349 r = dispc_mgr_lclk_rate(dispc, channel); in dispc_mgr_pclk_rate()
3353 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3357 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) in dispc_set_tv_pclk() argument
3359 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3362 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) in dispc_core_clk_rate() argument
3364 return dispc->core_clk_rate; in dispc_core_clk_rate()
3367 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, in dispc_plane_pclk_rate() argument
3375 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_pclk_rate()
3377 return dispc_mgr_pclk_rate(dispc, channel); in dispc_plane_pclk_rate()
3380 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, in dispc_plane_lclk_rate() argument
3388 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_lclk_rate()
3390 return dispc_mgr_lclk_rate(dispc, channel); in dispc_plane_lclk_rate()
3393 static void dispc_dump_clocks_channel(struct dispc_device *dispc, in dispc_dump_clocks_channel() argument
3402 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3407 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); in dispc_dump_clocks_channel()
3410 dispc_mgr_lclk_rate(dispc, channel), lcd); in dispc_dump_clocks_channel()
3412 dispc_mgr_pclk_rate(dispc, channel), pcd); in dispc_dump_clocks_channel()
3415 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) in dispc_dump_clocks() argument
3421 if (dispc_runtime_get(dispc)) in dispc_dump_clocks()
3426 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3430 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3432 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in dispc_dump_clocks()
3434 l = dispc_read_reg(dispc, DISPC_DIVISOR); in dispc_dump_clocks()
3438 (dispc_fclk_rate(dispc)/lcd), lcd); in dispc_dump_clocks()
3441 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); in dispc_dump_clocks()
3443 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_dump_clocks()
3444 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); in dispc_dump_clocks()
3445 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_dump_clocks()
3446 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); in dispc_dump_clocks()
3448 dispc_runtime_put(dispc); in dispc_dump_clocks()
3453 struct dispc_device *dispc = s->private; in dispc_dump_regs() local
3470 #define DUMPREG(dispc, r) \ in dispc_dump_regs() argument
3471 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3473 if (dispc_runtime_get(dispc)) in dispc_dump_regs()
3477 DUMPREG(dispc, DISPC_REVISION); in dispc_dump_regs()
3478 DUMPREG(dispc, DISPC_SYSCONFIG); in dispc_dump_regs()
3479 DUMPREG(dispc, DISPC_SYSSTATUS); in dispc_dump_regs()
3480 DUMPREG(dispc, DISPC_IRQSTATUS); in dispc_dump_regs()
3481 DUMPREG(dispc, DISPC_IRQENABLE); in dispc_dump_regs()
3482 DUMPREG(dispc, DISPC_CONTROL); in dispc_dump_regs()
3483 DUMPREG(dispc, DISPC_CONFIG); in dispc_dump_regs()
3484 DUMPREG(dispc, DISPC_CAPABLE); in dispc_dump_regs()
3485 DUMPREG(dispc, DISPC_LINE_STATUS); in dispc_dump_regs()
3486 DUMPREG(dispc, DISPC_LINE_NUMBER); in dispc_dump_regs()
3487 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_dump_regs()
3488 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_dump_regs()
3489 DUMPREG(dispc, DISPC_GLOBAL_ALPHA); in dispc_dump_regs()
3490 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_dump_regs()
3491 DUMPREG(dispc, DISPC_CONTROL2); in dispc_dump_regs()
3492 DUMPREG(dispc, DISPC_CONFIG2); in dispc_dump_regs()
3494 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_dump_regs()
3495 DUMPREG(dispc, DISPC_CONTROL3); in dispc_dump_regs()
3496 DUMPREG(dispc, DISPC_CONFIG3); in dispc_dump_regs()
3498 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3499 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); in dispc_dump_regs()
3504 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ in dispc_dump_regs() argument
3506 dispc_read_reg(dispc, DISPC_REG(i, r))) in dispc_dump_regs()
3511 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_dump_regs()
3512 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); in dispc_dump_regs()
3513 DUMPREG(dispc, i, DISPC_TRANS_COLOR); in dispc_dump_regs()
3514 DUMPREG(dispc, i, DISPC_SIZE_MGR); in dispc_dump_regs()
3519 DUMPREG(dispc, i, DISPC_TIMING_H); in dispc_dump_regs()
3520 DUMPREG(dispc, i, DISPC_TIMING_V); in dispc_dump_regs()
3521 DUMPREG(dispc, i, DISPC_POL_FREQ); in dispc_dump_regs()
3522 DUMPREG(dispc, i, DISPC_DIVISORo); in dispc_dump_regs()
3524 DUMPREG(dispc, i, DISPC_DATA_CYCLE1); in dispc_dump_regs()
3525 DUMPREG(dispc, i, DISPC_DATA_CYCLE2); in dispc_dump_regs()
3526 DUMPREG(dispc, i, DISPC_DATA_CYCLE3); in dispc_dump_regs()
3528 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_dump_regs()
3529 DUMPREG(dispc, i, DISPC_CPR_COEF_R); in dispc_dump_regs()
3530 DUMPREG(dispc, i, DISPC_CPR_COEF_G); in dispc_dump_regs()
3531 DUMPREG(dispc, i, DISPC_CPR_COEF_B); in dispc_dump_regs()
3537 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3538 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3539 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3540 DUMPREG(dispc, i, DISPC_OVL_POSITION); in dispc_dump_regs()
3541 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3542 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3543 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3544 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3545 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3546 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3548 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_dump_regs()
3549 DUMPREG(dispc, i, DISPC_OVL_PRELOAD); in dispc_dump_regs()
3550 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3551 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3554 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); in dispc_dump_regs()
3555 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); in dispc_dump_regs()
3559 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3560 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3561 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3562 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3563 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3564 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3565 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3566 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3567 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3568 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3570 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3571 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3574 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3576 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3577 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3578 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3579 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3580 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3581 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3582 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3583 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3585 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3586 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3588 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3589 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3590 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3591 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3592 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3593 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3594 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3595 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3596 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3597 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3599 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3600 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3607 #define DUMPREG(dispc, plane, name, i) \ in dispc_dump_regs() argument
3610 dispc_read_reg(dispc, DISPC_REG(plane, name, i))) in dispc_dump_regs()
3615 for (i = 1; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3617 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); in dispc_dump_regs()
3620 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); in dispc_dump_regs()
3623 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); in dispc_dump_regs()
3625 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_dump_regs()
3627 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); in dispc_dump_regs()
3630 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3632 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); in dispc_dump_regs()
3635 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); in dispc_dump_regs()
3638 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); in dispc_dump_regs()
3642 dispc_runtime_put(dispc); in dispc_dump_regs()
3651 int dispc_calc_clock_rates(struct dispc_device *dispc, in dispc_calc_clock_rates() argument
3666 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, in dispc_div_calc() argument
3684 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3687 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3710 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_div_calc()
3711 fck = dispc_core_clk_rate(dispc); in dispc_div_calc()
3726 void dispc_mgr_set_clock_div(struct dispc_device *dispc, in dispc_mgr_set_clock_div() argument
3733 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3737 int dispc_mgr_get_clock_div(struct dispc_device *dispc, in dispc_mgr_get_clock_div() argument
3743 fck = dispc_fclk_rate(dispc); in dispc_mgr_get_clock_div()
3745 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3746 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3754 static u32 dispc_read_irqstatus(struct dispc_device *dispc) in dispc_read_irqstatus() argument
3756 return dispc_read_reg(dispc, DISPC_IRQSTATUS); in dispc_read_irqstatus()
3759 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) in dispc_clear_irqstatus() argument
3761 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); in dispc_clear_irqstatus()
3764 static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) in dispc_write_irqenable() argument
3766 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3769 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_write_irqenable()
3771 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); in dispc_write_irqenable()
3774 dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3777 void dispc_enable_sidle(struct dispc_device *dispc) in dispc_enable_sidle() argument
3780 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); in dispc_enable_sidle()
3783 void dispc_disable_sidle(struct dispc_device *dispc) in dispc_disable_sidle() argument
3785 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ in dispc_disable_sidle()
3788 static u32 dispc_mgr_gamma_size(struct dispc_device *dispc, in dispc_mgr_gamma_size() argument
3793 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3799 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, in dispc_mgr_write_gamma_table() argument
3803 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3816 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3820 static void dispc_restore_gamma_tables(struct dispc_device *dispc) in dispc_restore_gamma_tables() argument
3824 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3827 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); in dispc_restore_gamma_tables()
3829 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); in dispc_restore_gamma_tables()
3831 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_gamma_tables()
3832 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); in dispc_restore_gamma_tables()
3834 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_gamma_tables()
3835 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); in dispc_restore_gamma_tables()
3843 static void dispc_mgr_set_gamma(struct dispc_device *dispc, in dispc_mgr_set_gamma() argument
3849 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3855 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3887 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3888 dispc_mgr_write_gamma_table(dispc, channel); in dispc_mgr_set_gamma()
3891 static int dispc_init_gamma_tables(struct dispc_device *dispc) in dispc_init_gamma_tables() argument
3895 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3898 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3903 !dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_init_gamma_tables()
3907 !dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_init_gamma_tables()
3910 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3915 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3917 dispc_mgr_set_gamma(dispc, channel, NULL, 0); in dispc_init_gamma_tables()
3922 static void _omap_dispc_initial_config(struct dispc_device *dispc) in _omap_dispc_initial_config() argument
3927 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in _omap_dispc_initial_config()
3928 l = dispc_read_reg(dispc, DISPC_DIVISOR); in _omap_dispc_initial_config()
3932 dispc_write_reg(dispc, DISPC_DIVISOR, l); in _omap_dispc_initial_config()
3934 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3938 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3939 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); in _omap_dispc_initial_config()
3945 if (dispc_has_feature(dispc, FEAT_FUNCGATED) || in _omap_dispc_initial_config()
3946 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3947 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); in _omap_dispc_initial_config()
3949 dispc_setup_color_conv_coef(dispc); in _omap_dispc_initial_config()
3951 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); in _omap_dispc_initial_config()
3953 dispc_init_fifos(dispc); in _omap_dispc_initial_config()
3955 dispc_configure_burst_sizes(dispc); in _omap_dispc_initial_config()
3957 dispc_ovl_enable_zorder_planes(dispc); in _omap_dispc_initial_config()
3959 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
3960 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); in _omap_dispc_initial_config()
3962 if (dispc_has_feature(dispc, FEAT_MFLAG)) in _omap_dispc_initial_config()
3963 dispc_init_mflag(dispc); in _omap_dispc_initial_config()
4482 struct dispc_device *dispc = arg; in dispc_irq_handler() local
4484 if (!dispc->is_enabled) in dispc_irq_handler()
4487 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4490 static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, in dispc_request_irq() argument
4495 if (dispc->user_handler != NULL) in dispc_request_irq()
4498 dispc->user_handler = handler; in dispc_request_irq()
4499 dispc->user_data = dev_id; in dispc_request_irq()
4504 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4505 IRQF_SHARED, "OMAP DISPC", dispc); in dispc_request_irq()
4507 dispc->user_handler = NULL; in dispc_request_irq()
4508 dispc->user_data = NULL; in dispc_request_irq()
4514 static void dispc_free_irq(struct dispc_device *dispc, void *dev_id) in dispc_free_irq() argument
4516 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4518 dispc->user_handler = NULL; in dispc_free_irq()
4519 dispc->user_data = NULL; in dispc_free_irq()
4522 static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) in dispc_get_memory_bandwidth_limit() argument
4527 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4604 static int dispc_errata_i734_wa_init(struct dispc_device *dispc) in dispc_errata_i734_wa_init() argument
4606 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4612 i734_buf.vaddr = dma_alloc_wc(&dispc->pdev->dev, i734_buf.size, in dispc_errata_i734_wa_init()
4615 dev_err(&dispc->pdev->dev, "%s: dma_alloc_wc failed\n", in dispc_errata_i734_wa_init()
4623 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) in dispc_errata_i734_wa_fini() argument
4625 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4628 dma_free_wc(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4632 static void dispc_errata_i734_wa(struct dispc_device *dispc) in dispc_errata_i734_wa() argument
4634 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, in dispc_errata_i734_wa()
4641 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4644 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); in dispc_errata_i734_wa()
4651 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); in dispc_errata_i734_wa()
4654 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, in dispc_errata_i734_wa()
4656 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); in dispc_errata_i734_wa()
4659 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); in dispc_errata_i734_wa()
4660 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4662 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); in dispc_errata_i734_wa()
4663 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); in dispc_errata_i734_wa()
4665 dispc_clear_irqstatus(dispc, framedone_irq); in dispc_errata_i734_wa()
4668 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); in dispc_errata_i734_wa()
4669 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); in dispc_errata_i734_wa()
4676 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { in dispc_errata_i734_wa()
4678 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4683 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); in dispc_errata_i734_wa()
4686 dispc_clear_irqstatus(dispc, 0xffffffff); in dispc_errata_i734_wa()
4689 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); in dispc_errata_i734_wa()
4757 struct dispc_device *dispc; in dispc_bind() local
4763 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); in dispc_bind()
4764 if (!dispc) in dispc_bind()
4767 dispc->pdev = pdev; in dispc_bind()
4768 platform_set_drvdata(pdev, dispc); in dispc_bind()
4769 dispc->dss = dss; in dispc_bind()
4771 spin_lock_init(&dispc->control_lock); in dispc_bind()
4779 dispc->feat = soc->data; in dispc_bind()
4781 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; in dispc_bind()
4783 r = dispc_errata_i734_wa_init(dispc); in dispc_bind()
4787 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0); in dispc_bind()
4788 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); in dispc_bind()
4789 if (IS_ERR(dispc->base)) { in dispc_bind()
4790 r = PTR_ERR(dispc->base); in dispc_bind()
4794 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4795 if (dispc->irq < 0) { in dispc_bind()
4802 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4803 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4805 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4810 &dispc->syscon_pol_offset)) { in dispc_bind()
4817 r = dispc_init_gamma_tables(dispc); in dispc_bind()
4823 r = dispc_runtime_get(dispc); in dispc_bind()
4827 _omap_dispc_initial_config(dispc); in dispc_bind()
4829 rev = dispc_read_reg(dispc, DISPC_REVISION); in dispc_bind()
4833 dispc_runtime_put(dispc); in dispc_bind()
4835 dss->dispc = dispc; in dispc_bind()
4838 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4839 dispc); in dispc_bind()
4846 kfree(dispc); in dispc_bind()
4852 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_unbind() local
4853 struct dss_device *dss = dispc->dss; in dispc_unbind()
4855 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4857 dss->dispc = NULL; in dispc_unbind()
4862 dispc_errata_i734_wa_fini(dispc); in dispc_unbind()
4864 kfree(dispc); in dispc_unbind()
4885 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_suspend() local
4887 dispc->is_enabled = false; in dispc_runtime_suspend()
4891 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4893 dispc_save_context(dispc); in dispc_runtime_suspend()
4900 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_resume() local
4908 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { in dispc_runtime_resume()
4909 _omap_dispc_initial_config(dispc); in dispc_runtime_resume()
4911 dispc_errata_i734_wa(dispc); in dispc_runtime_resume()
4913 dispc_restore_context(dispc); in dispc_runtime_resume()
4915 dispc_restore_gamma_tables(dispc); in dispc_runtime_resume()
4918 dispc->is_enabled = true; in dispc_runtime_resume()