344 					  XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);  in nv_crtc_mode_set_vga()
346 	regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |  in nv_crtc_mode_set_vga()
347 					  XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);  in nv_crtc_mode_set_vga()
349 	regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |  in nv_crtc_mode_set_vga()
350 					  XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |  in nv_crtc_mode_set_vga()
351 					  XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |  in nv_crtc_mode_set_vga()
353 					  XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |  in nv_crtc_mode_set_vga()
354 					  XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |  in nv_crtc_mode_set_vga()
355 					  XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |  in nv_crtc_mode_set_vga()
356 					  XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);  in nv_crtc_mode_set_vga()
360 					      XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);  in nv_crtc_mode_set_vga()
368 	regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);  in nv_crtc_mode_set_vga()
384 		XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);  in nv_crtc_mode_set_vga()
386 		XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);  in nv_crtc_mode_set_vga()
389 	regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |  in nv_crtc_mode_set_vga()
390 					   XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |  in nv_crtc_mode_set_vga()
391 					   XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |  in nv_crtc_mode_set_vga()
392 					   XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |  in nv_crtc_mode_set_vga()
393 					   XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);  in nv_crtc_mode_set_vga()
394 	regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |  in nv_crtc_mode_set_vga()
395 					    XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |  in nv_crtc_mode_set_vga()
396 					    XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |  in nv_crtc_mode_set_vga()
397 					    XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);  in nv_crtc_mode_set_vga()
398 	regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |  in nv_crtc_mode_set_vga()
399 					   XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |  in nv_crtc_mode_set_vga()
400 					   XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |  in nv_crtc_mode_set_vga()
401 					   XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);  in nv_crtc_mode_set_vga()
406 		regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);  in nv_crtc_mode_set_vga()
867 		XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);  in nv04_crtc_do_mode_set_base()
869 		XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);  in nv04_crtc_do_mode_set_base()