44 	int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
45 	int (*hw_init)(struct msm_gpu *gpu);
46 	int (*pm_suspend)(struct msm_gpu *gpu);
47 	int (*pm_resume)(struct msm_gpu *gpu);
48 	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
50 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
52 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
53 	void (*recover)(struct msm_gpu *gpu);
54 	void (*destroy)(struct msm_gpu *gpu);
57 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
60 	int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
62 	unsigned long (*gpu_busy)(struct msm_gpu *gpu);
63 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
65 	unsigned long (*gpu_get_freq)(struct msm_gpu *gpu);
66 	void (*gpu_set_freq)(struct msm_gpu *gpu, unsigned long freq);
144 static inline bool msm_gpu_active(struct msm_gpu *gpu)  in msm_gpu_active()  argument
148 	for (i = 0; i < gpu->nr_rings; i++) {  in msm_gpu_active()
149 		struct msm_ringbuffer *ring = gpu->rb[i];  in msm_gpu_active()
214 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)  in gpu_write()  argument
216 	msm_writel(data, gpu->mmio + (reg << 2));  in gpu_write()
219 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)  in gpu_read()  argument
221 	return msm_readl(gpu->mmio + (reg << 2));  in gpu_read()
224 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)  in gpu_rmw()  argument
226 	uint32_t val = gpu_read(gpu, reg);  in gpu_rmw()
229 	gpu_write(gpu, reg, val | or);  in gpu_rmw()
232 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)  in gpu_read64()  argument
250 	val = (u64) msm_readl(gpu->mmio + (lo << 2));  in gpu_read64()
251 	val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);  in gpu_read64()
256 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)  in gpu_write64()  argument
259 	msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));  in gpu_write64()
260 	msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));  in gpu_write64()
263 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
264 int msm_gpu_pm_resume(struct msm_gpu *gpu);
265 void msm_gpu_resume_devfreq(struct msm_gpu *gpu);
267 int msm_gpu_hw_init(struct msm_gpu *gpu);
269 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
270 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
271 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
274 void msm_gpu_retire(struct msm_gpu *gpu);
275 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
279 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
282 void msm_gpu_cleanup(struct msm_gpu *gpu);
294 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)  in msm_gpu_crashstate_get()  argument
298 	mutex_lock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_get()
300 	if (gpu->crashstate) {  in msm_gpu_crashstate_get()
301 		kref_get(&gpu->crashstate->ref);  in msm_gpu_crashstate_get()
302 		state = gpu->crashstate;  in msm_gpu_crashstate_get()
305 	mutex_unlock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_get()
310 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)  in msm_gpu_crashstate_put()  argument
312 	mutex_lock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_put()
314 	if (gpu->crashstate) {  in msm_gpu_crashstate_put()
315 		if (gpu->funcs->gpu_state_put(gpu->crashstate))  in msm_gpu_crashstate_put()
316 			gpu->crashstate = NULL;  in msm_gpu_crashstate_put()
319 	mutex_unlock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_put()