Lines Matching refs:ctrl
143 static int edp_clk_init(struct edp_ctrl *ctrl) in edp_clk_init() argument
145 struct platform_device *pdev = ctrl->pdev; in edp_clk_init()
148 ctrl->aux_clk = msm_clk_get(pdev, "core"); in edp_clk_init()
149 if (IS_ERR(ctrl->aux_clk)) { in edp_clk_init()
150 ret = PTR_ERR(ctrl->aux_clk); in edp_clk_init()
152 ctrl->aux_clk = NULL; in edp_clk_init()
156 ctrl->pixel_clk = msm_clk_get(pdev, "pixel"); in edp_clk_init()
157 if (IS_ERR(ctrl->pixel_clk)) { in edp_clk_init()
158 ret = PTR_ERR(ctrl->pixel_clk); in edp_clk_init()
160 ctrl->pixel_clk = NULL; in edp_clk_init()
164 ctrl->ahb_clk = msm_clk_get(pdev, "iface"); in edp_clk_init()
165 if (IS_ERR(ctrl->ahb_clk)) { in edp_clk_init()
166 ret = PTR_ERR(ctrl->ahb_clk); in edp_clk_init()
168 ctrl->ahb_clk = NULL; in edp_clk_init()
172 ctrl->link_clk = msm_clk_get(pdev, "link"); in edp_clk_init()
173 if (IS_ERR(ctrl->link_clk)) { in edp_clk_init()
174 ret = PTR_ERR(ctrl->link_clk); in edp_clk_init()
176 ctrl->link_clk = NULL; in edp_clk_init()
181 ctrl->mdp_core_clk = msm_clk_get(pdev, "mdp_core"); in edp_clk_init()
182 if (IS_ERR(ctrl->mdp_core_clk)) { in edp_clk_init()
183 ret = PTR_ERR(ctrl->mdp_core_clk); in edp_clk_init()
185 ctrl->mdp_core_clk = NULL; in edp_clk_init()
192 static int edp_clk_enable(struct edp_ctrl *ctrl, u32 clk_mask) in edp_clk_enable() argument
199 ret = clk_prepare_enable(ctrl->ahb_clk); in edp_clk_enable()
206 ret = clk_set_rate(ctrl->aux_clk, 19200000); in edp_clk_enable()
211 ret = clk_prepare_enable(ctrl->aux_clk); in edp_clk_enable()
220 (unsigned long)ctrl->link_rate * 27000000); in edp_clk_enable()
221 ret = clk_set_rate(ctrl->link_clk, in edp_clk_enable()
222 (unsigned long)ctrl->link_rate * 27000000); in edp_clk_enable()
229 ret = clk_prepare_enable(ctrl->link_clk); in edp_clk_enable()
237 (unsigned long)ctrl->pixel_rate * 1000); in edp_clk_enable()
238 ret = clk_set_rate(ctrl->pixel_clk, in edp_clk_enable()
239 (unsigned long)ctrl->pixel_rate * 1000); in edp_clk_enable()
246 ret = clk_prepare_enable(ctrl->pixel_clk); in edp_clk_enable()
253 ret = clk_prepare_enable(ctrl->mdp_core_clk); in edp_clk_enable()
264 clk_disable_unprepare(ctrl->pixel_clk); in edp_clk_enable()
267 clk_disable_unprepare(ctrl->link_clk); in edp_clk_enable()
270 clk_disable_unprepare(ctrl->aux_clk); in edp_clk_enable()
273 clk_disable_unprepare(ctrl->ahb_clk); in edp_clk_enable()
278 static void edp_clk_disable(struct edp_ctrl *ctrl, u32 clk_mask) in edp_clk_disable() argument
281 clk_disable_unprepare(ctrl->mdp_core_clk); in edp_clk_disable()
283 clk_disable_unprepare(ctrl->pixel_clk); in edp_clk_disable()
285 clk_disable_unprepare(ctrl->link_clk); in edp_clk_disable()
287 clk_disable_unprepare(ctrl->aux_clk); in edp_clk_disable()
289 clk_disable_unprepare(ctrl->ahb_clk); in edp_clk_disable()
292 static int edp_regulator_init(struct edp_ctrl *ctrl) in edp_regulator_init() argument
294 struct device *dev = &ctrl->pdev->dev; in edp_regulator_init()
298 ctrl->vdda_vreg = devm_regulator_get(dev, "vdda"); in edp_regulator_init()
299 ret = PTR_ERR_OR_ZERO(ctrl->vdda_vreg); in edp_regulator_init()
303 ctrl->vdda_vreg = NULL; in edp_regulator_init()
306 ctrl->lvl_vreg = devm_regulator_get(dev, "lvl-vdd"); in edp_regulator_init()
307 ret = PTR_ERR_OR_ZERO(ctrl->lvl_vreg); in edp_regulator_init()
311 ctrl->lvl_vreg = NULL; in edp_regulator_init()
318 static int edp_regulator_enable(struct edp_ctrl *ctrl) in edp_regulator_enable() argument
322 ret = regulator_set_load(ctrl->vdda_vreg, VDDA_UA_ON_LOAD); in edp_regulator_enable()
328 ret = regulator_enable(ctrl->vdda_vreg); in edp_regulator_enable()
334 ret = regulator_enable(ctrl->lvl_vreg); in edp_regulator_enable()
344 regulator_disable(ctrl->vdda_vreg); in edp_regulator_enable()
346 regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); in edp_regulator_enable()
351 static void edp_regulator_disable(struct edp_ctrl *ctrl) in edp_regulator_disable() argument
353 regulator_disable(ctrl->lvl_vreg); in edp_regulator_disable()
354 regulator_disable(ctrl->vdda_vreg); in edp_regulator_disable()
355 regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); in edp_regulator_disable()
358 static int edp_gpio_config(struct edp_ctrl *ctrl) in edp_gpio_config() argument
360 struct device *dev = &ctrl->pdev->dev; in edp_gpio_config()
363 ctrl->panel_hpd_gpio = devm_gpiod_get(dev, "panel-hpd", GPIOD_IN); in edp_gpio_config()
364 if (IS_ERR(ctrl->panel_hpd_gpio)) { in edp_gpio_config()
365 ret = PTR_ERR(ctrl->panel_hpd_gpio); in edp_gpio_config()
366 ctrl->panel_hpd_gpio = NULL; in edp_gpio_config()
371 ctrl->panel_en_gpio = devm_gpiod_get(dev, "panel-en", GPIOD_OUT_LOW); in edp_gpio_config()
372 if (IS_ERR(ctrl->panel_en_gpio)) { in edp_gpio_config()
373 ret = PTR_ERR(ctrl->panel_en_gpio); in edp_gpio_config()
374 ctrl->panel_en_gpio = NULL; in edp_gpio_config()
384 static void edp_ctrl_irq_enable(struct edp_ctrl *ctrl, int enable) in edp_ctrl_irq_enable() argument
389 spin_lock_irqsave(&ctrl->irq_lock, flags); in edp_ctrl_irq_enable()
391 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, EDP_INTR_MASK1); in edp_ctrl_irq_enable()
392 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, EDP_INTR_MASK2); in edp_ctrl_irq_enable()
394 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, 0x0); in edp_ctrl_irq_enable()
395 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, 0x0); in edp_ctrl_irq_enable()
397 spin_unlock_irqrestore(&ctrl->irq_lock, flags); in edp_ctrl_irq_enable()
401 static void edp_fill_link_cfg(struct edp_ctrl *ctrl) in edp_fill_link_cfg() argument
406 u8 max_lane = ctrl->dp_link.num_lanes; in edp_fill_link_cfg()
409 prate = ctrl->pixel_rate; in edp_fill_link_cfg()
410 bpp = ctrl->color_depth * 3; in edp_fill_link_cfg()
416 ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate); in edp_fill_link_cfg()
422 lrate *= ctrl->link_rate; in edp_fill_link_cfg()
431 ctrl->lane_cnt = lane; in edp_fill_link_cfg()
432 DBG("rate=%d lane=%d", ctrl->link_rate, ctrl->lane_cnt); in edp_fill_link_cfg()
435 static void edp_config_ctrl(struct edp_ctrl *ctrl) in edp_config_ctrl() argument
440 data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1); in edp_config_ctrl()
442 if (ctrl->dp_link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) in edp_config_ctrl()
446 if (ctrl->color_depth == 8) in edp_config_ctrl()
451 if (!ctrl->interlaced) /* progressive */ in edp_config_ctrl()
457 edp_write(ctrl->base + REG_EDP_CONFIGURATION_CTRL, data); in edp_config_ctrl()
460 static void edp_state_ctrl(struct edp_ctrl *ctrl, u32 state) in edp_state_ctrl() argument
462 edp_write(ctrl->base + REG_EDP_STATE_CTRL, state); in edp_state_ctrl()
467 static int edp_lane_set_write(struct edp_ctrl *ctrl, in edp_lane_set_write() argument
485 if (drm_dp_dpcd_write(ctrl->drm_aux, 0x103, buf, 4) < 4) { in edp_lane_set_write()
493 static int edp_train_pattern_set_write(struct edp_ctrl *ctrl, u8 pattern) in edp_train_pattern_set_write() argument
498 if (drm_dp_dpcd_write(ctrl->drm_aux, in edp_train_pattern_set_write()
507 static void edp_sink_train_set_adjust(struct edp_ctrl *ctrl, in edp_sink_train_set_adjust() argument
515 for (i = 0; i < ctrl->lane_cnt; i++) { in edp_sink_train_set_adjust()
522 ctrl->v_level = max >> DP_TRAIN_VOLTAGE_SWING_SHIFT; in edp_sink_train_set_adjust()
526 for (i = 0; i < ctrl->lane_cnt; i++) { in edp_sink_train_set_adjust()
533 ctrl->p_level = max >> DP_TRAIN_PRE_EMPHASIS_SHIFT; in edp_sink_train_set_adjust()
534 DBG("v_level=%d, p_level=%d", ctrl->v_level, ctrl->p_level); in edp_sink_train_set_adjust()
537 static void edp_host_train_set(struct edp_ctrl *ctrl, u32 train) in edp_host_train_set() argument
545 edp_state_ctrl(ctrl, EDP_STATE_CTRL_TRAIN_PATTERN_1 << shift); in edp_host_train_set()
547 data = edp_read(ctrl->base + REG_EDP_MAINLINK_READY); in edp_host_train_set()
571 static int edp_voltage_pre_emphasise_set(struct edp_ctrl *ctrl) in edp_voltage_pre_emphasise_set() argument
576 DBG("v=%d p=%d", ctrl->v_level, ctrl->p_level); in edp_voltage_pre_emphasise_set()
578 value0 = vm_pre_emphasis[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; in edp_voltage_pre_emphasise_set()
579 value1 = vm_voltage_swing[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; in edp_voltage_pre_emphasise_set()
583 msm_edp_phy_vm_pe_cfg(ctrl->phy, value0, value1); in edp_voltage_pre_emphasise_set()
584 return edp_lane_set_write(ctrl, ctrl->v_level, ctrl->p_level); in edp_voltage_pre_emphasise_set()
590 static int edp_start_link_train_1(struct edp_ctrl *ctrl) in edp_start_link_train_1() argument
600 edp_host_train_set(ctrl, DP_TRAINING_PATTERN_1); in edp_start_link_train_1()
601 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_1()
604 ret = edp_train_pattern_set_write(ctrl, in edp_start_link_train_1()
610 old_v_level = ctrl->v_level; in edp_start_link_train_1()
612 drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); in edp_start_link_train_1()
614 rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); in edp_start_link_train_1()
619 if (drm_dp_clock_recovery_ok(link_status, ctrl->lane_cnt)) { in edp_start_link_train_1()
624 if (ctrl->v_level == DPCD_LINK_VOLTAGE_MAX) { in edp_start_link_train_1()
629 if (old_v_level == ctrl->v_level) { in edp_start_link_train_1()
637 old_v_level = ctrl->v_level; in edp_start_link_train_1()
640 edp_sink_train_set_adjust(ctrl, link_status); in edp_start_link_train_1()
641 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_1()
649 static int edp_start_link_train_2(struct edp_ctrl *ctrl) in edp_start_link_train_2() argument
658 edp_host_train_set(ctrl, DP_TRAINING_PATTERN_2); in edp_start_link_train_2()
659 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_2()
663 ret = edp_train_pattern_set_write(ctrl, in edp_start_link_train_2()
669 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_start_link_train_2()
671 rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); in edp_start_link_train_2()
676 if (drm_dp_channel_eq_ok(link_status, ctrl->lane_cnt)) { in edp_start_link_train_2()
687 edp_sink_train_set_adjust(ctrl, link_status); in edp_start_link_train_2()
688 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_2()
696 static int edp_link_rate_down_shift(struct edp_ctrl *ctrl) in edp_link_rate_down_shift() argument
702 rate = ctrl->link_rate; in edp_link_rate_down_shift()
703 lane = ctrl->lane_cnt; in edp_link_rate_down_shift()
704 max_lane = ctrl->dp_link.num_lanes; in edp_link_rate_down_shift()
706 bpp = ctrl->color_depth * 3; in edp_link_rate_down_shift()
707 prate = ctrl->pixel_rate; in edp_link_rate_down_shift()
727 ctrl->pixel_rate, in edp_link_rate_down_shift()
731 ctrl->link_rate = rate; in edp_link_rate_down_shift()
732 ctrl->lane_cnt = lane; in edp_link_rate_down_shift()
741 static int edp_clear_training_pattern(struct edp_ctrl *ctrl) in edp_clear_training_pattern() argument
745 ret = edp_train_pattern_set_write(ctrl, 0); in edp_clear_training_pattern()
747 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_clear_training_pattern()
752 static int edp_do_link_train(struct edp_ctrl *ctrl) in edp_do_link_train() argument
762 dp_link.num_lanes = ctrl->lane_cnt; in edp_do_link_train()
763 dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate); in edp_do_link_train()
764 dp_link.capabilities = ctrl->dp_link.capabilities; in edp_do_link_train()
765 if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0) in edp_do_link_train()
768 ctrl->v_level = 0; /* start from default level */ in edp_do_link_train()
769 ctrl->p_level = 0; in edp_do_link_train()
771 edp_state_ctrl(ctrl, 0); in edp_do_link_train()
772 if (edp_clear_training_pattern(ctrl)) in edp_do_link_train()
775 ret = edp_start_link_train_1(ctrl); in edp_do_link_train()
777 if (edp_link_rate_down_shift(ctrl) == 0) { in edp_do_link_train()
789 edp_state_ctrl(ctrl, 0); in edp_do_link_train()
790 if (edp_clear_training_pattern(ctrl)) in edp_do_link_train()
793 ret = edp_start_link_train_2(ctrl); in edp_do_link_train()
795 if (edp_link_rate_down_shift(ctrl) == 0) { in edp_do_link_train()
807 edp_state_ctrl(ctrl, EDP_STATE_CTRL_SEND_VIDEO); in edp_do_link_train()
809 edp_clear_training_pattern(ctrl); in edp_do_link_train()
814 static void edp_clock_synchrous(struct edp_ctrl *ctrl, int sync) in edp_clock_synchrous() argument
819 data = edp_read(ctrl->base + REG_EDP_MISC1_MISC0); in edp_clock_synchrous()
828 if (ctrl->color_depth == 8) in edp_clock_synchrous()
830 else if (ctrl->color_depth == 10) in edp_clock_synchrous()
832 else if (ctrl->color_depth == 12) in edp_clock_synchrous()
834 else if (ctrl->color_depth == 16) in edp_clock_synchrous()
839 edp_write(ctrl->base + REG_EDP_MISC1_MISC0, data); in edp_clock_synchrous()
842 static int edp_sw_mvid_nvid(struct edp_ctrl *ctrl, u32 m, u32 n) in edp_sw_mvid_nvid() argument
846 if (ctrl->link_rate == DP_LINK_BW_1_62) { in edp_sw_mvid_nvid()
848 } else if (ctrl->link_rate == DP_LINK_BW_2_7) { in edp_sw_mvid_nvid()
852 ctrl->link_rate); in edp_sw_mvid_nvid()
856 edp_write(ctrl->base + REG_EDP_SOFTWARE_MVID, m * m_multi); in edp_sw_mvid_nvid()
857 edp_write(ctrl->base + REG_EDP_SOFTWARE_NVID, n * n_multi); in edp_sw_mvid_nvid()
862 static void edp_mainlink_ctrl(struct edp_ctrl *ctrl, int enable) in edp_mainlink_ctrl() argument
866 edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, EDP_MAINLINK_CTRL_RESET); in edp_mainlink_ctrl()
874 edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, data); in edp_mainlink_ctrl()
877 static void edp_ctrl_phy_aux_enable(struct edp_ctrl *ctrl, int enable) in edp_ctrl_phy_aux_enable() argument
880 edp_regulator_enable(ctrl); in edp_ctrl_phy_aux_enable()
881 edp_clk_enable(ctrl, EDP_CLK_MASK_AUX_CHAN); in edp_ctrl_phy_aux_enable()
882 msm_edp_phy_ctrl(ctrl->phy, 1); in edp_ctrl_phy_aux_enable()
883 msm_edp_aux_ctrl(ctrl->aux, 1); in edp_ctrl_phy_aux_enable()
884 gpiod_set_value(ctrl->panel_en_gpio, 1); in edp_ctrl_phy_aux_enable()
886 gpiod_set_value(ctrl->panel_en_gpio, 0); in edp_ctrl_phy_aux_enable()
887 msm_edp_aux_ctrl(ctrl->aux, 0); in edp_ctrl_phy_aux_enable()
888 msm_edp_phy_ctrl(ctrl->phy, 0); in edp_ctrl_phy_aux_enable()
889 edp_clk_disable(ctrl, EDP_CLK_MASK_AUX_CHAN); in edp_ctrl_phy_aux_enable()
890 edp_regulator_disable(ctrl); in edp_ctrl_phy_aux_enable()
894 static void edp_ctrl_link_enable(struct edp_ctrl *ctrl, int enable) in edp_ctrl_link_enable() argument
900 edp_clk_enable(ctrl, EDP_CLK_MASK_LINK_CHAN); in edp_ctrl_link_enable()
902 msm_edp_phy_lane_power_ctrl(ctrl->phy, true, ctrl->lane_cnt); in edp_ctrl_link_enable()
904 msm_edp_phy_vm_pe_init(ctrl->phy); in edp_ctrl_link_enable()
908 msm_edp_phy_ready(ctrl->phy); in edp_ctrl_link_enable()
910 edp_config_ctrl(ctrl); in edp_ctrl_link_enable()
911 msm_edp_ctrl_pixel_clock_valid(ctrl, ctrl->pixel_rate, &m, &n); in edp_ctrl_link_enable()
912 edp_sw_mvid_nvid(ctrl, m, n); in edp_ctrl_link_enable()
913 edp_mainlink_ctrl(ctrl, 1); in edp_ctrl_link_enable()
915 edp_mainlink_ctrl(ctrl, 0); in edp_ctrl_link_enable()
917 msm_edp_phy_lane_power_ctrl(ctrl->phy, false, 0); in edp_ctrl_link_enable()
918 edp_clk_disable(ctrl, EDP_CLK_MASK_LINK_CHAN); in edp_ctrl_link_enable()
922 static int edp_ctrl_training(struct edp_ctrl *ctrl) in edp_ctrl_training() argument
927 if (!ctrl->power_on) in edp_ctrl_training()
931 ret = edp_do_link_train(ctrl); in edp_ctrl_training()
934 edp_ctrl_irq_enable(ctrl, 0); in edp_ctrl_training()
935 edp_ctrl_link_enable(ctrl, 0); in edp_ctrl_training()
936 msm_edp_phy_ctrl(ctrl->phy, 0); in edp_ctrl_training()
942 msm_edp_phy_ctrl(ctrl->phy, 1); in edp_ctrl_training()
943 edp_ctrl_link_enable(ctrl, 1); in edp_ctrl_training()
944 edp_ctrl_irq_enable(ctrl, 1); in edp_ctrl_training()
953 struct edp_ctrl *ctrl = container_of( in edp_ctrl_on_worker() local
957 mutex_lock(&ctrl->dev_mutex); in edp_ctrl_on_worker()
959 if (ctrl->power_on) { in edp_ctrl_on_worker()
964 edp_ctrl_phy_aux_enable(ctrl, 1); in edp_ctrl_on_worker()
965 edp_ctrl_link_enable(ctrl, 1); in edp_ctrl_on_worker()
967 edp_ctrl_irq_enable(ctrl, 1); in edp_ctrl_on_worker()
968 ret = drm_dp_link_power_up(ctrl->drm_aux, &ctrl->dp_link); in edp_ctrl_on_worker()
972 ctrl->power_on = true; in edp_ctrl_on_worker()
975 ret = edp_ctrl_training(ctrl); in edp_ctrl_on_worker()
983 edp_ctrl_irq_enable(ctrl, 0); in edp_ctrl_on_worker()
984 edp_ctrl_link_enable(ctrl, 0); in edp_ctrl_on_worker()
985 edp_ctrl_phy_aux_enable(ctrl, 0); in edp_ctrl_on_worker()
986 ctrl->power_on = false; in edp_ctrl_on_worker()
988 mutex_unlock(&ctrl->dev_mutex); in edp_ctrl_on_worker()
993 struct edp_ctrl *ctrl = container_of( in edp_ctrl_off_worker() local
997 mutex_lock(&ctrl->dev_mutex); in edp_ctrl_off_worker()
999 if (!ctrl->power_on) { in edp_ctrl_off_worker()
1004 reinit_completion(&ctrl->idle_comp); in edp_ctrl_off_worker()
1005 edp_state_ctrl(ctrl, EDP_STATE_CTRL_PUSH_IDLE); in edp_ctrl_off_worker()
1007 time_left = wait_for_completion_timeout(&ctrl->idle_comp, in edp_ctrl_off_worker()
1012 edp_state_ctrl(ctrl, 0); in edp_ctrl_off_worker()
1014 drm_dp_link_power_down(ctrl->drm_aux, &ctrl->dp_link); in edp_ctrl_off_worker()
1016 edp_ctrl_irq_enable(ctrl, 0); in edp_ctrl_off_worker()
1018 edp_ctrl_link_enable(ctrl, 0); in edp_ctrl_off_worker()
1020 edp_ctrl_phy_aux_enable(ctrl, 0); in edp_ctrl_off_worker()
1022 ctrl->power_on = false; in edp_ctrl_off_worker()
1025 mutex_unlock(&ctrl->dev_mutex); in edp_ctrl_off_worker()
1028 irqreturn_t msm_edp_ctrl_irq(struct edp_ctrl *ctrl) in msm_edp_ctrl_irq() argument
1034 spin_lock(&ctrl->irq_lock); in msm_edp_ctrl_irq()
1035 isr1 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_1); in msm_edp_ctrl_irq()
1036 isr2 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_2); in msm_edp_ctrl_irq()
1050 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, ack); in msm_edp_ctrl_irq()
1055 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, ack); in msm_edp_ctrl_irq()
1056 spin_unlock(&ctrl->irq_lock); in msm_edp_ctrl_irq()
1066 complete(&ctrl->idle_comp); in msm_edp_ctrl_irq()
1069 msm_edp_aux_irq(ctrl->aux, isr1); in msm_edp_ctrl_irq()
1074 void msm_edp_ctrl_power(struct edp_ctrl *ctrl, bool on) in msm_edp_ctrl_power() argument
1077 queue_work(ctrl->workqueue, &ctrl->on_work); in msm_edp_ctrl_power()
1079 queue_work(ctrl->workqueue, &ctrl->off_work); in msm_edp_ctrl_power()
1084 struct edp_ctrl *ctrl = NULL; in msm_edp_ctrl_init() local
1093 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in msm_edp_ctrl_init()
1094 if (!ctrl) in msm_edp_ctrl_init()
1097 edp->ctrl = ctrl; in msm_edp_ctrl_init()
1098 ctrl->pdev = edp->pdev; in msm_edp_ctrl_init()
1100 ctrl->base = msm_ioremap(ctrl->pdev, "edp", "eDP"); in msm_edp_ctrl_init()
1101 if (IS_ERR(ctrl->base)) in msm_edp_ctrl_init()
1102 return PTR_ERR(ctrl->base); in msm_edp_ctrl_init()
1105 ret = edp_regulator_init(ctrl); in msm_edp_ctrl_init()
1110 ret = edp_clk_init(ctrl); in msm_edp_ctrl_init()
1115 ret = edp_gpio_config(ctrl); in msm_edp_ctrl_init()
1122 ctrl->aux = msm_edp_aux_init(dev, ctrl->base, &ctrl->drm_aux); in msm_edp_ctrl_init()
1123 if (!ctrl->aux || !ctrl->drm_aux) { in msm_edp_ctrl_init()
1128 ctrl->phy = msm_edp_phy_init(dev, ctrl->base); in msm_edp_ctrl_init()
1129 if (!ctrl->phy) { in msm_edp_ctrl_init()
1135 spin_lock_init(&ctrl->irq_lock); in msm_edp_ctrl_init()
1136 mutex_init(&ctrl->dev_mutex); in msm_edp_ctrl_init()
1137 init_completion(&ctrl->idle_comp); in msm_edp_ctrl_init()
1140 ctrl->workqueue = alloc_ordered_workqueue("edp_drm_work", 0); in msm_edp_ctrl_init()
1141 INIT_WORK(&ctrl->on_work, edp_ctrl_on_worker); in msm_edp_ctrl_init()
1142 INIT_WORK(&ctrl->off_work, edp_ctrl_off_worker); in msm_edp_ctrl_init()
1147 msm_edp_aux_destroy(dev, ctrl->aux); in msm_edp_ctrl_init()
1148 ctrl->aux = NULL; in msm_edp_ctrl_init()
1152 void msm_edp_ctrl_destroy(struct edp_ctrl *ctrl) in msm_edp_ctrl_destroy() argument
1154 if (!ctrl) in msm_edp_ctrl_destroy()
1157 if (ctrl->workqueue) { in msm_edp_ctrl_destroy()
1158 flush_workqueue(ctrl->workqueue); in msm_edp_ctrl_destroy()
1159 destroy_workqueue(ctrl->workqueue); in msm_edp_ctrl_destroy()
1160 ctrl->workqueue = NULL; in msm_edp_ctrl_destroy()
1163 if (ctrl->aux) { in msm_edp_ctrl_destroy()
1164 msm_edp_aux_destroy(&ctrl->pdev->dev, ctrl->aux); in msm_edp_ctrl_destroy()
1165 ctrl->aux = NULL; in msm_edp_ctrl_destroy()
1168 kfree(ctrl->edid); in msm_edp_ctrl_destroy()
1169 ctrl->edid = NULL; in msm_edp_ctrl_destroy()
1171 mutex_destroy(&ctrl->dev_mutex); in msm_edp_ctrl_destroy()
1174 bool msm_edp_ctrl_panel_connected(struct edp_ctrl *ctrl) in msm_edp_ctrl_panel_connected() argument
1176 mutex_lock(&ctrl->dev_mutex); in msm_edp_ctrl_panel_connected()
1177 DBG("connect status = %d", ctrl->edp_connected); in msm_edp_ctrl_panel_connected()
1178 if (ctrl->edp_connected) { in msm_edp_ctrl_panel_connected()
1179 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_panel_connected()
1183 if (!ctrl->power_on) { in msm_edp_ctrl_panel_connected()
1184 edp_ctrl_phy_aux_enable(ctrl, 1); in msm_edp_ctrl_panel_connected()
1185 edp_ctrl_irq_enable(ctrl, 1); in msm_edp_ctrl_panel_connected()
1188 if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, in msm_edp_ctrl_panel_connected()
1191 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); in msm_edp_ctrl_panel_connected()
1193 ctrl->edp_connected = true; in msm_edp_ctrl_panel_connected()
1196 if (!ctrl->power_on) { in msm_edp_ctrl_panel_connected()
1197 edp_ctrl_irq_enable(ctrl, 0); in msm_edp_ctrl_panel_connected()
1198 edp_ctrl_phy_aux_enable(ctrl, 0); in msm_edp_ctrl_panel_connected()
1201 DBG("exit: connect status=%d", ctrl->edp_connected); in msm_edp_ctrl_panel_connected()
1203 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_panel_connected()
1205 return ctrl->edp_connected; in msm_edp_ctrl_panel_connected()
1208 int msm_edp_ctrl_get_panel_info(struct edp_ctrl *ctrl, in msm_edp_ctrl_get_panel_info() argument
1213 mutex_lock(&ctrl->dev_mutex); in msm_edp_ctrl_get_panel_info()
1215 if (ctrl->edid) { in msm_edp_ctrl_get_panel_info()
1218 *edid = ctrl->edid; in msm_edp_ctrl_get_panel_info()
1223 if (!ctrl->power_on) { in msm_edp_ctrl_get_panel_info()
1224 edp_ctrl_phy_aux_enable(ctrl, 1); in msm_edp_ctrl_get_panel_info()
1225 edp_ctrl_irq_enable(ctrl, 1); in msm_edp_ctrl_get_panel_info()
1228 ret = drm_dp_link_probe(ctrl->drm_aux, &ctrl->dp_link); in msm_edp_ctrl_get_panel_info()
1235 ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate); in msm_edp_ctrl_get_panel_info()
1237 ctrl->edid = drm_get_edid(connector, &ctrl->drm_aux->ddc); in msm_edp_ctrl_get_panel_info()
1238 if (!ctrl->edid) { in msm_edp_ctrl_get_panel_info()
1244 *edid = ctrl->edid; in msm_edp_ctrl_get_panel_info()
1247 if (!ctrl->power_on) { in msm_edp_ctrl_get_panel_info()
1248 edp_ctrl_irq_enable(ctrl, 0); in msm_edp_ctrl_get_panel_info()
1249 edp_ctrl_phy_aux_enable(ctrl, 0); in msm_edp_ctrl_get_panel_info()
1252 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_get_panel_info()
1256 int msm_edp_ctrl_timing_cfg(struct edp_ctrl *ctrl, in msm_edp_ctrl_timing_cfg() argument
1264 mutex_lock(&ctrl->dev_mutex); in msm_edp_ctrl_timing_cfg()
1269 ctrl->color_depth = info->bpc; in msm_edp_ctrl_timing_cfg()
1270 ctrl->pixel_rate = mode->clock; in msm_edp_ctrl_timing_cfg()
1271 ctrl->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); in msm_edp_ctrl_timing_cfg()
1274 edp_fill_link_cfg(ctrl); in msm_edp_ctrl_timing_cfg()
1276 if (edp_clk_enable(ctrl, EDP_CLK_MASK_AHB)) { in msm_edp_ctrl_timing_cfg()
1281 edp_clock_synchrous(ctrl, 1); in msm_edp_ctrl_timing_cfg()
1284 edp_write(ctrl->base + REG_EDP_TOTAL_HOR_VER, in msm_edp_ctrl_timing_cfg()
1290 edp_write(ctrl->base + REG_EDP_START_HOR_VER_FROM_SYNC, in msm_edp_ctrl_timing_cfg()
1302 edp_write(ctrl->base + REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY, data); in msm_edp_ctrl_timing_cfg()
1304 edp_write(ctrl->base + REG_EDP_ACTIVE_HOR_VER, in msm_edp_ctrl_timing_cfg()
1308 edp_clk_disable(ctrl, EDP_CLK_MASK_AHB); in msm_edp_ctrl_timing_cfg()
1311 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_timing_cfg()
1315 bool msm_edp_ctrl_pixel_clock_valid(struct edp_ctrl *ctrl, in msm_edp_ctrl_pixel_clock_valid() argument
1323 if (ctrl->link_rate == DP_LINK_BW_1_62) { in msm_edp_ctrl_pixel_clock_valid()
1325 } else if (ctrl->link_rate == DP_LINK_BW_2_7) { in msm_edp_ctrl_pixel_clock_valid()
1328 pr_err("%s: Invalid link rate,%d\n", __func__, ctrl->link_rate); in msm_edp_ctrl_pixel_clock_valid()