190 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)  in dsi_write()  function
777 	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);  in dsi_intr_ctrl()
824 		dsi_write(msm_host, REG_DSI_CTRL, 0);  in dsi_ctrl_config()
845 		dsi_write(msm_host, REG_DSI_VID_CFG0, data);  in dsi_ctrl_config()
849 		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);  in dsi_ctrl_config()
854 		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);  in dsi_ctrl_config()
861 		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);  in dsi_ctrl_config()
864 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,  in dsi_ctrl_config()
877 	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);  in dsi_ctrl_config()
881 	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);  in dsi_ctrl_config()
886 		dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,  in dsi_ctrl_config()
892 	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);  in dsi_ctrl_config()
895 	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);  in dsi_ctrl_config()
899 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_ctrl_config()
906 	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
910 		dsi_write(msm_host, REG_DSI_LANE_CTRL,  in dsi_ctrl_config()
915 	dsi_write(msm_host, REG_DSI_CTRL, data);  in dsi_ctrl_config()
951 		dsi_write(msm_host, REG_DSI_ACTIVE_H,  in dsi_timing_setup()
954 		dsi_write(msm_host, REG_DSI_ACTIVE_V,  in dsi_timing_setup()
957 		dsi_write(msm_host, REG_DSI_TOTAL,  in dsi_timing_setup()
961 		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,  in dsi_timing_setup()
964 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);  in dsi_timing_setup()
965 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,  in dsi_timing_setup()
972 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,  in dsi_timing_setup()
979 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,  in dsi_timing_setup()
987 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset()
990 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset()
992 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset()
1017 	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);  in dsi_op_mode_config()
1031 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);  in dsi_set_tx_power_mode()
1389 	dsi_write(msm_host, REG_DSI_CTRL, data1);  in dsi_sw_reset_restore()
1396 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset_restore()
1400 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset_restore()
1402 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset_restore()
1404 	dsi_write(msm_host, REG_DSI_CTRL, data0);  in dsi_sw_reset_restore()
1440 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);  in dsi_ack_err_status()
1442 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);  in dsi_ack_err_status()
1454 		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);  in dsi_timeout_status()
1470 		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);  in dsi_dln0_phy_err()
1483 		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);  in dsi_fifo_status()
1498 		dsi_write(msm_host, REG_DSI_STATUS0, status);  in dsi_status()
1511 		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);  in dsi_clk_status()
1542 	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);  in dsi_host_irq()
2008 	dsi_write(msm_host, REG_DSI_CTRL,  in msm_dsi_host_xfer_prepare()
2024 	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);  in msm_dsi_host_xfer_restore()
2092 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,  in msm_dsi_host_cmd_rx()
2095 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);  in msm_dsi_host_cmd_rx()
2183 	dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);  in msm_dsi_host_cmd_xfer_commit()
2184 	dsi_write(msm_host, REG_DSI_DMA_LEN, len);  in msm_dsi_host_cmd_xfer_commit()
2185 	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);  in msm_dsi_host_cmd_xfer_commit()
2247 	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);  in msm_dsi_host_reset_phy()
2251 	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);  in msm_dsi_host_reset_phy()