113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val)  in DSI_6G_HW_VERSION_MAJOR()
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val)  in DSI_6G_HW_VERSION_MINOR()
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val)  in DSI_6G_HW_VERSION_STEP()
156 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)  in DSI_VID_CFG0_VIRT_CHANNEL()
162 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val)  in DSI_VID_CFG0_DST_FORMAT()
168 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)  in DSI_VID_CFG0_TRAFFIC_MODE()
185 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)  in DSI_VID_CFG1_RGB_SWAP()
193 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)  in DSI_ACTIVE_H_START()
199 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)  in DSI_ACTIVE_H_END()
207 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)  in DSI_ACTIVE_V_START()
213 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)  in DSI_ACTIVE_V_END()
221 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)  in DSI_TOTAL_H_TOTAL()
227 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)  in DSI_TOTAL_V_TOTAL()
235 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)  in DSI_ACTIVE_HSYNC_START()
241 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)  in DSI_ACTIVE_HSYNC_END()
249 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val)  in DSI_ACTIVE_VSYNC_HPOS_START()
255 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val)  in DSI_ACTIVE_VSYNC_HPOS_END()
263 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val)  in DSI_ACTIVE_VSYNC_VPOS_START()
269 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val)  in DSI_ACTIVE_VSYNC_VPOS_END()
282 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val)  in DSI_CMD_CFG0_DST_FORMAT()
291 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val)  in DSI_CMD_CFG0_INTERLEAVE_MAX()
297 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val)  in DSI_CMD_CFG0_RGB_SWAP()
305 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val)  in DSI_CMD_CFG1_WR_MEM_START()
311 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val)  in DSI_CMD_CFG1_WR_MEM_CONTINUE()
324 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val)  in DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE()
330 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val)  in DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL()
336 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val)  in DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT()
344 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val)  in DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL()
350 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val)  in DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL()
357 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }  in REG_DSI_RDBK()
359 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }  in REG_DSI_RDBK_DATA()
364 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)  in DSI_TRIG_CTRL_DMA_TRIGGER()
370 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)  in DSI_TRIG_CTRL_MDP_TRIGGER()
376 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val)  in DSI_TRIG_CTRL_STREAM()
397 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)  in DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE()
403 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)  in DSI_CLKOUT_TIMING_CTRL_T_CLK_POST()
418 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val)  in DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL()
450 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val)  in DSI_RDBK_DATA_CTRL_COUNT()
459 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)  in DSI_VERSION_MAJOR()
571 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN()
573 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_0()
575 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_1()
577 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_28nm_8960_PHY_LN_CFG_2()
579 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x…  in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
581 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*…  in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
583 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*…  in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
600 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO()
608 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL()
616 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE()
626 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT()
634 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO()
642 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE()
650 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL()
658 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST()
666 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO()
672 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE()
680 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET()
688 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD()
800 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN()
802 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_0()
804 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_1()
806 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_2()
808 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_3()
810 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_CFG_4()
812 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0…  in REG_DSI_28nm_PHY_LN_TEST_DATAPATH()
814 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_DEBUG_SEL()
816 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_TEST_STR_0()
818 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }  in REG_DSI_28nm_PHY_LN_TEST_STR_1()
841 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO()
849 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
857 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
868 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT()
876 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO()
884 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE()
892 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL()
900 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST()
908 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_9_TA_GO()
914 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE()
922 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_10_TA_GET()
930 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
1017 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV()
1026 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET()
1032 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN()
1040 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0()
1048 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val)  in DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8()
1127 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN()
1129 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_0()
1131 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_1()
1133 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_2()
1135 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_3()
1137 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_CFG_4()
1139 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0…  in REG_DSI_20nm_PHY_LN_TEST_DATAPATH()
1141 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_DEBUG_SEL()
1143 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_TEST_STR_0()
1145 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }  in REG_DSI_20nm_PHY_LN_TEST_STR_1()
1168 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO()
1176 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
1184 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
1195 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT()
1203 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO()
1211 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE()
1219 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL()
1227 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST()
1235 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_9_TA_GO()
1241 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE()
1249 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_10_TA_GET()
1257 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
1318 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val)  in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0()
1324 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val)  in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4()
1363 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val)  in DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL()
1368 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN()
1370 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG0()
1373 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val)  in DSI_14nm_PHY_LN_CFG0_PREPARE_DLY()
1378 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG1()
1381 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG2()
1383 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_CFG3()
1385 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TEST_DATAPATH()
1387 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_TEST_STR()
1389 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_4()
1392 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT()
1397 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_5()
1400 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO()
1405 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_6()
1408 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE()
1413 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_7()
1416 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL()
1421 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_8()
1424 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST()
1429 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_9()
1432 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO()
1438 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE()
1443 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_10()
1446 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET()
1451 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i…  in REG_DSI_14nm_PHY_LN_TIMING_CTRL_11()
1454 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)  in DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD()
1459 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*…  in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0()
1461 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*…  in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1()
1463 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; }  in REG_DSI_14nm_PHY_LN_VREG_CNTRL()
1629 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN()
1631 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG0()
1633 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG1()
1635 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG2()
1637 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_CFG3()
1639 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_TEST_DATAPATH()
1641 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_PIN_SWAP()
1643 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL()
1645 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL()
1647 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*…  in REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL()
1649 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0…  in REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL()
1651 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_LPRX_CTRL()
1653 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; }  in REG_DSI_10nm_PHY_LN_TX_DCTRL()