Lines Matching refs:val
113 static inline uint32_t DSI_6G_HW_VERSION_MAJOR(uint32_t val) in DSI_6G_HW_VERSION_MAJOR() argument
115 return ((val) << DSI_6G_HW_VERSION_MAJOR__SHIFT) & DSI_6G_HW_VERSION_MAJOR__MASK; in DSI_6G_HW_VERSION_MAJOR()
119 static inline uint32_t DSI_6G_HW_VERSION_MINOR(uint32_t val) in DSI_6G_HW_VERSION_MINOR() argument
121 return ((val) << DSI_6G_HW_VERSION_MINOR__SHIFT) & DSI_6G_HW_VERSION_MINOR__MASK; in DSI_6G_HW_VERSION_MINOR()
125 static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) in DSI_6G_HW_VERSION_STEP() argument
127 return ((val) << DSI_6G_HW_VERSION_STEP__SHIFT) & DSI_6G_HW_VERSION_STEP__MASK; in DSI_6G_HW_VERSION_STEP()
156 static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val) in DSI_VID_CFG0_VIRT_CHANNEL() argument
158 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK; in DSI_VID_CFG0_VIRT_CHANNEL()
162 static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_vid_dst_format val) in DSI_VID_CFG0_DST_FORMAT() argument
164 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK; in DSI_VID_CFG0_DST_FORMAT()
168 static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) in DSI_VID_CFG0_TRAFFIC_MODE() argument
170 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK; in DSI_VID_CFG0_TRAFFIC_MODE()
185 static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val) in DSI_VID_CFG1_RGB_SWAP() argument
187 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK; in DSI_VID_CFG1_RGB_SWAP()
193 static inline uint32_t DSI_ACTIVE_H_START(uint32_t val) in DSI_ACTIVE_H_START() argument
195 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK; in DSI_ACTIVE_H_START()
199 static inline uint32_t DSI_ACTIVE_H_END(uint32_t val) in DSI_ACTIVE_H_END() argument
201 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK; in DSI_ACTIVE_H_END()
207 static inline uint32_t DSI_ACTIVE_V_START(uint32_t val) in DSI_ACTIVE_V_START() argument
209 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK; in DSI_ACTIVE_V_START()
213 static inline uint32_t DSI_ACTIVE_V_END(uint32_t val) in DSI_ACTIVE_V_END() argument
215 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK; in DSI_ACTIVE_V_END()
221 static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val) in DSI_TOTAL_H_TOTAL() argument
223 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK; in DSI_TOTAL_H_TOTAL()
227 static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val) in DSI_TOTAL_V_TOTAL() argument
229 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK; in DSI_TOTAL_V_TOTAL()
235 static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val) in DSI_ACTIVE_HSYNC_START() argument
237 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK; in DSI_ACTIVE_HSYNC_START()
241 static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val) in DSI_ACTIVE_HSYNC_END() argument
243 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK; in DSI_ACTIVE_HSYNC_END()
249 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_START(uint32_t val) in DSI_ACTIVE_VSYNC_HPOS_START() argument
251 return ((val) << DSI_ACTIVE_VSYNC_HPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_START__MASK; in DSI_ACTIVE_VSYNC_HPOS_START()
255 static inline uint32_t DSI_ACTIVE_VSYNC_HPOS_END(uint32_t val) in DSI_ACTIVE_VSYNC_HPOS_END() argument
257 return ((val) << DSI_ACTIVE_VSYNC_HPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_HPOS_END__MASK; in DSI_ACTIVE_VSYNC_HPOS_END()
263 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_START(uint32_t val) in DSI_ACTIVE_VSYNC_VPOS_START() argument
265 return ((val) << DSI_ACTIVE_VSYNC_VPOS_START__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_START__MASK; in DSI_ACTIVE_VSYNC_VPOS_START()
269 static inline uint32_t DSI_ACTIVE_VSYNC_VPOS_END(uint32_t val) in DSI_ACTIVE_VSYNC_VPOS_END() argument
271 return ((val) << DSI_ACTIVE_VSYNC_VPOS_END__SHIFT) & DSI_ACTIVE_VSYNC_VPOS_END__MASK; in DSI_ACTIVE_VSYNC_VPOS_END()
282 static inline uint32_t DSI_CMD_CFG0_DST_FORMAT(enum dsi_cmd_dst_format val) in DSI_CMD_CFG0_DST_FORMAT() argument
284 return ((val) << DSI_CMD_CFG0_DST_FORMAT__SHIFT) & DSI_CMD_CFG0_DST_FORMAT__MASK; in DSI_CMD_CFG0_DST_FORMAT()
291 static inline uint32_t DSI_CMD_CFG0_INTERLEAVE_MAX(uint32_t val) in DSI_CMD_CFG0_INTERLEAVE_MAX() argument
293 return ((val) << DSI_CMD_CFG0_INTERLEAVE_MAX__SHIFT) & DSI_CMD_CFG0_INTERLEAVE_MAX__MASK; in DSI_CMD_CFG0_INTERLEAVE_MAX()
297 static inline uint32_t DSI_CMD_CFG0_RGB_SWAP(enum dsi_rgb_swap val) in DSI_CMD_CFG0_RGB_SWAP() argument
299 return ((val) << DSI_CMD_CFG0_RGB_SWAP__SHIFT) & DSI_CMD_CFG0_RGB_SWAP__MASK; in DSI_CMD_CFG0_RGB_SWAP()
305 static inline uint32_t DSI_CMD_CFG1_WR_MEM_START(uint32_t val) in DSI_CMD_CFG1_WR_MEM_START() argument
307 return ((val) << DSI_CMD_CFG1_WR_MEM_START__SHIFT) & DSI_CMD_CFG1_WR_MEM_START__MASK; in DSI_CMD_CFG1_WR_MEM_START()
311 static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) in DSI_CMD_CFG1_WR_MEM_CONTINUE() argument
313 return ((val) << DSI_CMD_CFG1_WR_MEM_CONTINUE__SHIFT) & DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK; in DSI_CMD_CFG1_WR_MEM_CONTINUE()
324 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) in DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE() argument
326 …return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MA… in DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE()
330 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) in DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL() argument
332 …return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL… in DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL()
336 static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) in DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT() argument
338 …return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__… in DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT()
344 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) in DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL() argument
346 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; in DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL()
350 static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) in DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL() argument
352 return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; in DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL()
364 static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val) in DSI_TRIG_CTRL_DMA_TRIGGER() argument
366 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK; in DSI_TRIG_CTRL_DMA_TRIGGER()
370 static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val) in DSI_TRIG_CTRL_MDP_TRIGGER() argument
372 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK; in DSI_TRIG_CTRL_MDP_TRIGGER()
376 static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) in DSI_TRIG_CTRL_STREAM() argument
378 return ((val) << DSI_TRIG_CTRL_STREAM__SHIFT) & DSI_TRIG_CTRL_STREAM__MASK; in DSI_TRIG_CTRL_STREAM()
397 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val) in DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE() argument
399 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK; in DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE()
403 static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) in DSI_CLKOUT_TIMING_CTRL_T_CLK_POST() argument
405 …return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MA… in DSI_CLKOUT_TIMING_CTRL_T_CLK_POST()
418 static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) in DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL() argument
420 return ((val) << DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT) & DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK; in DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL()
450 static inline uint32_t DSI_RDBK_DATA_CTRL_COUNT(uint32_t val) in DSI_RDBK_DATA_CTRL_COUNT() argument
452 return ((val) << DSI_RDBK_DATA_CTRL_COUNT__SHIFT) & DSI_RDBK_DATA_CTRL_COUNT__MASK; in DSI_RDBK_DATA_CTRL_COUNT()
459 static inline uint32_t DSI_VERSION_MAJOR(uint32_t val) in DSI_VERSION_MAJOR() argument
461 return ((val) << DSI_VERSION_MAJOR__SHIFT) & DSI_VERSION_MAJOR__MASK; in DSI_VERSION_MAJOR()
600 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO() argument
602 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_… in DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO()
608 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL() argument
610 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL… in DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL()
616 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE() argument
618 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CT… in DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE()
626 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT() argument
628 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_4… in DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT()
634 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO() argument
636 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_5… in DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO()
642 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE() argument
644 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTR… in DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE()
650 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL() argument
652 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_… in DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL()
658 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST() argument
660 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_8… in DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST()
666 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO() argument
668 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9_T… in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO()
672 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE() argument
674 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_9… in DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE()
680 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET() argument
682 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTRL_1… in DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET()
688 static inline uint32_t DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) in DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD() argument
690 …return ((val) << DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_8960_PHY_TIMING_CTR… in DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD()
841 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO() argument
843 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO… in DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO()
849 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL() argument
851 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRA… in DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
857 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE() argument
859 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_2_CLK_P… in DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
868 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT() argument
870 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__… in DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT()
876 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO() argument
878 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__… in DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO()
884 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE() argument
886 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_6_HS_PRE… in DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE()
892 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL() argument
894 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL… in DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL()
900 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST() argument
902 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__… in DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST()
908 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_9_TA_GO() argument
910 return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK; in DSI_28nm_PHY_TIMING_CTRL_9_TA_GO()
914 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE() argument
916 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__… in DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE()
922 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_10_TA_GET() argument
924 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__… in DSI_28nm_PHY_TIMING_CTRL_10_TA_GET()
930 static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) in DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD() argument
932 …return ((val) << DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_28nm_PHY_TIMING_CTRL_11_TRIG3… in DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
1017 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV() argument
1019 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MA… in DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV()
1026 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET() argument
1028 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET… in DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET()
1032 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN() argument
1034 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN… in DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN()
1040 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0() argument
1042 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_… in DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0()
1048 static inline uint32_t DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8(uint32_t val) in DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8() argument
1050 …return ((val) << DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT) & DSI_28nm_PHY_PLL_SDM_CFG3_FREQ… in DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8()
1168 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO() argument
1170 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO… in DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO()
1176 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL() argument
1178 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRA… in DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL()
1184 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE() argument
1186 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_P… in DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE()
1195 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT() argument
1197 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__… in DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT()
1203 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO() argument
1205 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__… in DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO()
1211 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE() argument
1213 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PRE… in DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE()
1219 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL() argument
1221 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL… in DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL()
1227 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST() argument
1229 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__… in DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST()
1235 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_9_TA_GO() argument
1237 return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK; in DSI_20nm_PHY_TIMING_CTRL_9_TA_GO()
1241 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE() argument
1243 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__… in DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE()
1249 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_10_TA_GET() argument
1251 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__… in DSI_20nm_PHY_TIMING_CTRL_10_TA_GET()
1257 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) in DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD() argument
1259 …return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3… in DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD()
1318 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(uint32_t val) in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0() argument
1320 …return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CT… in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0()
1324 static inline uint32_t DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(uint32_t val) in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4() argument
1326 …return ((val) << DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT) & DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CT… in DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4()
1363 static inline uint32_t DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL(uint32_t val) in DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL() argument
1365 …return ((val) << DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT) & DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CT… in DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL()
1373 static inline uint32_t DSI_14nm_PHY_LN_CFG0_PREPARE_DLY(uint32_t val) in DSI_14nm_PHY_LN_CFG0_PREPARE_DLY() argument
1375 return ((val) << DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__SHIFT) & DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK; in DSI_14nm_PHY_LN_CFG0_PREPARE_DLY()
1392 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT() argument
1394 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_… in DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT()
1400 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO() argument
1402 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_… in DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO()
1408 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE() argument
1410 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_6_… in DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE()
1416 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL() argument
1418 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_7_HS… in DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL()
1424 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST() argument
1426 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_… in DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST()
1432 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO() argument
1434 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO… in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO()
1438 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE() argument
1440 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_… in DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE()
1446 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET() argument
1448 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_10_TA… in DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET()
1454 static inline uint32_t DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD(uint32_t val) in DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD() argument
1456 …return ((val) << DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_14nm_PHY_LN_TIMING_CTRL_11… in DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD()