113 static inline uint32_t MDP4_VERSION_MINOR(uint32_t val)  in MDP4_VERSION_MINOR()  argument
115 	return ((val) << MDP4_VERSION_MINOR__SHIFT) & MDP4_VERSION_MINOR__MASK;  in MDP4_VERSION_MINOR()
119 static inline uint32_t MDP4_VERSION_MAJOR(uint32_t val)  in MDP4_VERSION_MAJOR()  argument
121 	return ((val) << MDP4_VERSION_MAJOR__SHIFT) & MDP4_VERSION_MAJOR__MASK;  in MDP4_VERSION_MAJOR()
141 static inline uint32_t MDP4_DISP_INTF_SEL_PRIM(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_PRIM()  argument
143 	return ((val) << MDP4_DISP_INTF_SEL_PRIM__SHIFT) & MDP4_DISP_INTF_SEL_PRIM__MASK;  in MDP4_DISP_INTF_SEL_PRIM()
147 static inline uint32_t MDP4_DISP_INTF_SEL_SEC(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_SEC()  argument
149 	return ((val) << MDP4_DISP_INTF_SEL_SEC__SHIFT) & MDP4_DISP_INTF_SEL_SEC__MASK;  in MDP4_DISP_INTF_SEL_SEC()
153 static inline uint32_t MDP4_DISP_INTF_SEL_EXT(enum mdp4_intf val)  in MDP4_DISP_INTF_SEL_EXT()  argument
155 	return ((val) << MDP4_DISP_INTF_SEL_EXT__SHIFT) & MDP4_DISP_INTF_SEL_EXT__MASK;  in MDP4_DISP_INTF_SEL_EXT()
183 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()  argument
185 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE0__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE0()
190 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()  argument
192 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE1__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE1()
197 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()  argument
199 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE2__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE2()
204 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()  argument
206 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE3__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE3()
211 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()  argument
213 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE4__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE4()
218 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()  argument
220 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE5__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE5()
225 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()  argument
227 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE6__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE6()
232 static inline uint32_t MDP4_LAYERMIXER2_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()  argument
234 	return ((val) << MDP4_LAYERMIXER2_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER2_IN_CFG_PIPE7__MASK;  in MDP4_LAYERMIXER2_IN_CFG_PIPE7()
243 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE0(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE0()  argument
245 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE0__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE0()
250 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE1(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE1()  argument
252 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE1__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE1()
257 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE2(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE2()  argument
259 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE2__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE2()
264 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE3(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE3()  argument
266 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE3__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE3()
271 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE4(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE4()  argument
273 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE4__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE4()
278 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE5(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE5()  argument
280 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE5__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE5()
285 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE6(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE6()  argument
287 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE6__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE6()
292 static inline uint32_t MDP4_LAYERMIXER_IN_CFG_PIPE7(enum mdp_mixer_stage_id val)  in MDP4_LAYERMIXER_IN_CFG_PIPE7()  argument
294 	return ((val) << MDP4_LAYERMIXER_IN_CFG_PIPE7__SHIFT) & MDP4_LAYERMIXER_IN_CFG_PIPE7__MASK;  in MDP4_LAYERMIXER_IN_CFG_PIPE7()
326 static inline uint32_t MDP4_OVLP_SIZE_HEIGHT(uint32_t val)  in MDP4_OVLP_SIZE_HEIGHT()  argument
328 	return ((val) << MDP4_OVLP_SIZE_HEIGHT__SHIFT) & MDP4_OVLP_SIZE_HEIGHT__MASK;  in MDP4_OVLP_SIZE_HEIGHT()
332 static inline uint32_t MDP4_OVLP_SIZE_WIDTH(uint32_t val)  in MDP4_OVLP_SIZE_WIDTH()  argument
334 	return ((val) << MDP4_OVLP_SIZE_WIDTH__SHIFT) & MDP4_OVLP_SIZE_WIDTH__MASK;  in MDP4_OVLP_SIZE_WIDTH()
358 static inline uint32_t MDP4_OVLP_STAGE_OP_FG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_FG_ALPHA()  argument
360 	return ((val) << MDP4_OVLP_STAGE_OP_FG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_FG_ALPHA__MASK;  in MDP4_OVLP_STAGE_OP_FG_ALPHA()
366 static inline uint32_t MDP4_OVLP_STAGE_OP_BG_ALPHA(enum mdp_alpha_type val)  in MDP4_OVLP_STAGE_OP_BG_ALPHA()  argument
368 	return ((val) << MDP4_OVLP_STAGE_OP_BG_ALPHA__SHIFT) & MDP4_OVLP_STAGE_OP_BG_ALPHA__MASK;  in MDP4_OVLP_STAGE_OP_BG_ALPHA()
461 static inline uint32_t MDP4_DMA_CONFIG_G_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_G_BPC()  argument
463 	return ((val) << MDP4_DMA_CONFIG_G_BPC__SHIFT) & MDP4_DMA_CONFIG_G_BPC__MASK;  in MDP4_DMA_CONFIG_G_BPC()
467 static inline uint32_t MDP4_DMA_CONFIG_B_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_B_BPC()  argument
469 	return ((val) << MDP4_DMA_CONFIG_B_BPC__SHIFT) & MDP4_DMA_CONFIG_B_BPC__MASK;  in MDP4_DMA_CONFIG_B_BPC()
473 static inline uint32_t MDP4_DMA_CONFIG_R_BPC(enum mdp_bpc val)  in MDP4_DMA_CONFIG_R_BPC()  argument
475 	return ((val) << MDP4_DMA_CONFIG_R_BPC__SHIFT) & MDP4_DMA_CONFIG_R_BPC__MASK;  in MDP4_DMA_CONFIG_R_BPC()
480 static inline uint32_t MDP4_DMA_CONFIG_PACK(uint32_t val)  in MDP4_DMA_CONFIG_PACK()  argument
482 	return ((val) << MDP4_DMA_CONFIG_PACK__SHIFT) & MDP4_DMA_CONFIG_PACK__MASK;  in MDP4_DMA_CONFIG_PACK()
490 static inline uint32_t MDP4_DMA_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_SRC_SIZE_HEIGHT()  argument
492 	return ((val) << MDP4_DMA_SRC_SIZE_HEIGHT__SHIFT) & MDP4_DMA_SRC_SIZE_HEIGHT__MASK;  in MDP4_DMA_SRC_SIZE_HEIGHT()
496 static inline uint32_t MDP4_DMA_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_SRC_SIZE_WIDTH()  argument
498 	return ((val) << MDP4_DMA_SRC_SIZE_WIDTH__SHIFT) & MDP4_DMA_SRC_SIZE_WIDTH__MASK;  in MDP4_DMA_SRC_SIZE_WIDTH()
508 static inline uint32_t MDP4_DMA_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_DST_SIZE_HEIGHT()  argument
510 	return ((val) << MDP4_DMA_DST_SIZE_HEIGHT__SHIFT) & MDP4_DMA_DST_SIZE_HEIGHT__MASK;  in MDP4_DMA_DST_SIZE_HEIGHT()
514 static inline uint32_t MDP4_DMA_DST_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_DST_SIZE_WIDTH()  argument
516 	return ((val) << MDP4_DMA_DST_SIZE_WIDTH__SHIFT) & MDP4_DMA_DST_SIZE_WIDTH__MASK;  in MDP4_DMA_DST_SIZE_WIDTH()
522 static inline uint32_t MDP4_DMA_CURSOR_SIZE_WIDTH(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_WIDTH()  argument
524 	return ((val) << MDP4_DMA_CURSOR_SIZE_WIDTH__SHIFT) & MDP4_DMA_CURSOR_SIZE_WIDTH__MASK;  in MDP4_DMA_CURSOR_SIZE_WIDTH()
528 static inline uint32_t MDP4_DMA_CURSOR_SIZE_HEIGHT(uint32_t val)  in MDP4_DMA_CURSOR_SIZE_HEIGHT()  argument
530 	return ((val) << MDP4_DMA_CURSOR_SIZE_HEIGHT__SHIFT) & MDP4_DMA_CURSOR_SIZE_HEIGHT__MASK;  in MDP4_DMA_CURSOR_SIZE_HEIGHT()
538 static inline uint32_t MDP4_DMA_CURSOR_POS_X(uint32_t val)  in MDP4_DMA_CURSOR_POS_X()  argument
540 	return ((val) << MDP4_DMA_CURSOR_POS_X__SHIFT) & MDP4_DMA_CURSOR_POS_X__MASK;  in MDP4_DMA_CURSOR_POS_X()
544 static inline uint32_t MDP4_DMA_CURSOR_POS_Y(uint32_t val)  in MDP4_DMA_CURSOR_POS_Y()  argument
546 	return ((val) << MDP4_DMA_CURSOR_POS_Y__SHIFT) & MDP4_DMA_CURSOR_POS_Y__MASK;  in MDP4_DMA_CURSOR_POS_Y()
553 static inline uint32_t MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(enum mdp4_cursor_format val)  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()  argument
555 …return ((val) << MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT__SHIFT) & MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT…  in MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT()
595 static inline uint32_t MDP4_PIPE_SRC_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SRC_SIZE_HEIGHT()  argument
597 	return ((val) << MDP4_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SRC_SIZE_HEIGHT__MASK;  in MDP4_PIPE_SRC_SIZE_HEIGHT()
601 static inline uint32_t MDP4_PIPE_SRC_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SRC_SIZE_WIDTH()  argument
603 	return ((val) << MDP4_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SRC_SIZE_WIDTH__MASK;  in MDP4_PIPE_SRC_SIZE_WIDTH()
609 static inline uint32_t MDP4_PIPE_SRC_XY_Y(uint32_t val)  in MDP4_PIPE_SRC_XY_Y()  argument
611 	return ((val) << MDP4_PIPE_SRC_XY_Y__SHIFT) & MDP4_PIPE_SRC_XY_Y__MASK;  in MDP4_PIPE_SRC_XY_Y()
615 static inline uint32_t MDP4_PIPE_SRC_XY_X(uint32_t val)  in MDP4_PIPE_SRC_XY_X()  argument
617 	return ((val) << MDP4_PIPE_SRC_XY_X__SHIFT) & MDP4_PIPE_SRC_XY_X__MASK;  in MDP4_PIPE_SRC_XY_X()
623 static inline uint32_t MDP4_PIPE_DST_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_DST_SIZE_HEIGHT()  argument
625 	return ((val) << MDP4_PIPE_DST_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_DST_SIZE_HEIGHT__MASK;  in MDP4_PIPE_DST_SIZE_HEIGHT()
629 static inline uint32_t MDP4_PIPE_DST_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_DST_SIZE_WIDTH()  argument
631 	return ((val) << MDP4_PIPE_DST_SIZE_WIDTH__SHIFT) & MDP4_PIPE_DST_SIZE_WIDTH__MASK;  in MDP4_PIPE_DST_SIZE_WIDTH()
637 static inline uint32_t MDP4_PIPE_DST_XY_Y(uint32_t val)  in MDP4_PIPE_DST_XY_Y()  argument
639 	return ((val) << MDP4_PIPE_DST_XY_Y__SHIFT) & MDP4_PIPE_DST_XY_Y__MASK;  in MDP4_PIPE_DST_XY_Y()
643 static inline uint32_t MDP4_PIPE_DST_XY_X(uint32_t val)  in MDP4_PIPE_DST_XY_X()  argument
645 	return ((val) << MDP4_PIPE_DST_XY_X__SHIFT) & MDP4_PIPE_DST_XY_X__MASK;  in MDP4_PIPE_DST_XY_X()
659 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P0(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P0()  argument
661 	return ((val) << MDP4_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P0__MASK;  in MDP4_PIPE_SRC_STRIDE_A_P0()
665 static inline uint32_t MDP4_PIPE_SRC_STRIDE_A_P1(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_A_P1()  argument
667 	return ((val) << MDP4_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP4_PIPE_SRC_STRIDE_A_P1__MASK;  in MDP4_PIPE_SRC_STRIDE_A_P1()
673 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P2(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P2()  argument
675 	return ((val) << MDP4_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P2__MASK;  in MDP4_PIPE_SRC_STRIDE_B_P2()
679 static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)  in MDP4_PIPE_SRC_STRIDE_B_P3()  argument
681 	return ((val) << MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP4_PIPE_SRC_STRIDE_B_P3__MASK;  in MDP4_PIPE_SRC_STRIDE_B_P3()
687 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT(uint32_t val)  in MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT()  argument
689 …return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT__…  in MDP4_PIPE_SSTILE_FRAME_SIZE_HEIGHT()
693 static inline uint32_t MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH(uint32_t val)  in MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH()  argument
695 …return ((val) << MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__SHIFT) & MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH__MA…  in MDP4_PIPE_SSTILE_FRAME_SIZE_WIDTH()
701 static inline uint32_t MDP4_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_G_BPC()  argument
703 	return ((val) << MDP4_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_G_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_G_BPC()
707 static inline uint32_t MDP4_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_B_BPC()  argument
709 	return ((val) << MDP4_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_B_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_B_BPC()
713 static inline uint32_t MDP4_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val)  in MDP4_PIPE_SRC_FORMAT_R_BPC()  argument
715 	return ((val) << MDP4_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_R_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_R_BPC()
719 static inline uint32_t MDP4_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val)  in MDP4_PIPE_SRC_FORMAT_A_BPC()  argument
721 	return ((val) << MDP4_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP4_PIPE_SRC_FORMAT_A_BPC__MASK;  in MDP4_PIPE_SRC_FORMAT_A_BPC()
726 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CPP(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_CPP()  argument
728 	return ((val) << MDP4_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CPP__MASK;  in MDP4_PIPE_SRC_FORMAT_CPP()
733 static inline uint32_t MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()  argument
735 …return ((val) << MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT__MA…  in MDP4_PIPE_SRC_FORMAT_UNPACK_COUNT()
741 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FETCH_PLANES(uint32_t val)  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()  argument
743 …return ((val) << MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__SHIFT) & MDP4_PIPE_SRC_FORMAT_FETCH_PLANES__MA…  in MDP4_PIPE_SRC_FORMAT_FETCH_PLANES()
748 static inline uint32_t MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp_chroma_samp_type val)  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()  argument
750 	return ((val) << MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK;  in MDP4_PIPE_SRC_FORMAT_CHROMA_SAMP()
754 static inline uint32_t MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT(enum mdp4_frame_format val)  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()  argument
756 …return ((val) << MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__SHIFT) & MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT__MA…  in MDP4_PIPE_SRC_FORMAT_FRAME_FORMAT()
762 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM0(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM0()  argument
764 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM0__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM0()
768 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM1(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM1()  argument
770 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM1__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM1()
774 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM2(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM2()  argument
776 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM2__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM2()
780 static inline uint32_t MDP4_PIPE_SRC_UNPACK_ELEM3(uint32_t val)  in MDP4_PIPE_SRC_UNPACK_ELEM3()  argument
782 	return ((val) << MDP4_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP4_PIPE_SRC_UNPACK_ELEM3__MASK;  in MDP4_PIPE_SRC_UNPACK_ELEM3()
790 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()  argument
792 …return ((val) << MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL__MA…  in MDP4_PIPE_OP_MODE_SCALEX_UNIT_SEL()
796 static inline uint32_t MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL(enum mdp4_scale_unit val)  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()  argument
798 …return ((val) << MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__SHIFT) & MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL__MA…  in MDP4_PIPE_OP_MODE_SCALEY_UNIT_SEL()
848 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PULSEW()  argument
850 	return ((val) << MDP4_LCDC_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PULSEW__MASK;  in MDP4_LCDC_HSYNC_CTRL_PULSEW()
854 static inline uint32_t MDP4_LCDC_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_LCDC_HSYNC_CTRL_PERIOD()  argument
856 	return ((val) << MDP4_LCDC_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_LCDC_HSYNC_CTRL_PERIOD__MASK;  in MDP4_LCDC_HSYNC_CTRL_PERIOD()
866 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_START()  argument
868 	return ((val) << MDP4_LCDC_DISPLAY_HCTRL_START__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_START__MASK;  in MDP4_LCDC_DISPLAY_HCTRL_START()
872 static inline uint32_t MDP4_LCDC_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_LCDC_DISPLAY_HCTRL_END()  argument
874 	return ((val) << MDP4_LCDC_DISPLAY_HCTRL_END__SHIFT) & MDP4_LCDC_DISPLAY_HCTRL_END__MASK;  in MDP4_LCDC_DISPLAY_HCTRL_END()
884 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_START(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_START()  argument
886 	return ((val) << MDP4_LCDC_ACTIVE_HCTL_START__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_START__MASK;  in MDP4_LCDC_ACTIVE_HCTL_START()
890 static inline uint32_t MDP4_LCDC_ACTIVE_HCTL_END(uint32_t val)  in MDP4_LCDC_ACTIVE_HCTL_END()  argument
892 	return ((val) << MDP4_LCDC_ACTIVE_HCTL_END__SHIFT) & MDP4_LCDC_ACTIVE_HCTL_END__MASK;  in MDP4_LCDC_ACTIVE_HCTL_END()
905 static inline uint32_t MDP4_LCDC_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()  argument
907 	return ((val) << MDP4_LCDC_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_LCDC_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_LCDC_UNDERFLOW_CLR_COLOR()
943 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()  argument
945 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT0()
949 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()  argument
951 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT1()
955 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()  argument
957 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT2()
961 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()  argument
963 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3__…  in MDP4_LCDC_LVDS_MUX_CTL_3_TO_0_BIT3()
969 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()  argument
971 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT4()
975 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()  argument
977 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT5()
981 static inline uint32_t MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6(uint32_t val)  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()  argument
983 …return ((val) << MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__SHIFT) & MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6__…  in MDP4_LCDC_LVDS_MUX_CTL_6_TO_4_BIT6()
1022 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PULSEW()  argument
1024 	return ((val) << MDP4_DTV_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DTV_HSYNC_CTRL_PULSEW__MASK;  in MDP4_DTV_HSYNC_CTRL_PULSEW()
1028 static inline uint32_t MDP4_DTV_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DTV_HSYNC_CTRL_PERIOD()  argument
1030 	return ((val) << MDP4_DTV_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DTV_HSYNC_CTRL_PERIOD__MASK;  in MDP4_DTV_HSYNC_CTRL_PERIOD()
1040 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_START()  argument
1042 	return ((val) << MDP4_DTV_DISPLAY_HCTRL_START__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_START__MASK;  in MDP4_DTV_DISPLAY_HCTRL_START()
1046 static inline uint32_t MDP4_DTV_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DTV_DISPLAY_HCTRL_END()  argument
1048 	return ((val) << MDP4_DTV_DISPLAY_HCTRL_END__SHIFT) & MDP4_DTV_DISPLAY_HCTRL_END__MASK;  in MDP4_DTV_DISPLAY_HCTRL_END()
1058 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_START()  argument
1060 	return ((val) << MDP4_DTV_ACTIVE_HCTL_START__SHIFT) & MDP4_DTV_ACTIVE_HCTL_START__MASK;  in MDP4_DTV_ACTIVE_HCTL_START()
1064 static inline uint32_t MDP4_DTV_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DTV_ACTIVE_HCTL_END()  argument
1066 	return ((val) << MDP4_DTV_ACTIVE_HCTL_END__SHIFT) & MDP4_DTV_ACTIVE_HCTL_END__MASK;  in MDP4_DTV_ACTIVE_HCTL_END()
1079 static inline uint32_t MDP4_DTV_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DTV_UNDERFLOW_CLR_COLOR()  argument
1081 	return ((val) << MDP4_DTV_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DTV_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_DTV_UNDERFLOW_CLR_COLOR()
1101 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PULSEW(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PULSEW()  argument
1103 	return ((val) << MDP4_DSI_HSYNC_CTRL_PULSEW__SHIFT) & MDP4_DSI_HSYNC_CTRL_PULSEW__MASK;  in MDP4_DSI_HSYNC_CTRL_PULSEW()
1107 static inline uint32_t MDP4_DSI_HSYNC_CTRL_PERIOD(uint32_t val)  in MDP4_DSI_HSYNC_CTRL_PERIOD()  argument
1109 	return ((val) << MDP4_DSI_HSYNC_CTRL_PERIOD__SHIFT) & MDP4_DSI_HSYNC_CTRL_PERIOD__MASK;  in MDP4_DSI_HSYNC_CTRL_PERIOD()
1119 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_START(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_START()  argument
1121 	return ((val) << MDP4_DSI_DISPLAY_HCTRL_START__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_START__MASK;  in MDP4_DSI_DISPLAY_HCTRL_START()
1125 static inline uint32_t MDP4_DSI_DISPLAY_HCTRL_END(uint32_t val)  in MDP4_DSI_DISPLAY_HCTRL_END()  argument
1127 	return ((val) << MDP4_DSI_DISPLAY_HCTRL_END__SHIFT) & MDP4_DSI_DISPLAY_HCTRL_END__MASK;  in MDP4_DSI_DISPLAY_HCTRL_END()
1137 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_START(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_START()  argument
1139 	return ((val) << MDP4_DSI_ACTIVE_HCTL_START__SHIFT) & MDP4_DSI_ACTIVE_HCTL_START__MASK;  in MDP4_DSI_ACTIVE_HCTL_START()
1143 static inline uint32_t MDP4_DSI_ACTIVE_HCTL_END(uint32_t val)  in MDP4_DSI_ACTIVE_HCTL_END()  argument
1145 	return ((val) << MDP4_DSI_ACTIVE_HCTL_END__SHIFT) & MDP4_DSI_ACTIVE_HCTL_END__MASK;  in MDP4_DSI_ACTIVE_HCTL_END()
1158 static inline uint32_t MDP4_DSI_UNDERFLOW_CLR_COLOR(uint32_t val)  in MDP4_DSI_UNDERFLOW_CLR_COLOR()  argument
1160 	return ((val) << MDP4_DSI_UNDERFLOW_CLR_COLOR__SHIFT) & MDP4_DSI_UNDERFLOW_CLR_COLOR__MASK;  in MDP4_DSI_UNDERFLOW_CLR_COLOR()