380 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE_0_DST_OFF()  argument
382 	return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;  in CP_LOAD_STATE_0_DST_OFF()
386 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)  in CP_LOAD_STATE_0_STATE_SRC()  argument
388 	return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;  in CP_LOAD_STATE_0_STATE_SRC()
392 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)  in CP_LOAD_STATE_0_STATE_BLOCK()  argument
394 	return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE_0_STATE_BLOCK()
398 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE_0_NUM_UNIT()  argument
400 	return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;  in CP_LOAD_STATE_0_NUM_UNIT()
406 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)  in CP_LOAD_STATE_1_STATE_TYPE()  argument
408 	return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;  in CP_LOAD_STATE_1_STATE_TYPE()
412 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE_1_EXT_SRC_ADDR()  argument
414 	return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE_1_EXT_SRC_ADDR()
420 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE4_0_DST_OFF()  argument
422 	return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;  in CP_LOAD_STATE4_0_DST_OFF()
426 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)  in CP_LOAD_STATE4_0_STATE_SRC()  argument
428 	return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;  in CP_LOAD_STATE4_0_STATE_SRC()
432 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)  in CP_LOAD_STATE4_0_STATE_BLOCK()  argument
434 	return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE4_0_STATE_BLOCK()
438 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE4_0_NUM_UNIT()  argument
440 	return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;  in CP_LOAD_STATE4_0_NUM_UNIT()
446 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)  in CP_LOAD_STATE4_1_STATE_TYPE()  argument
448 	return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;  in CP_LOAD_STATE4_1_STATE_TYPE()
452 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()  argument
454 	return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE4_1_EXT_SRC_ADDR()
460 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()  argument
462 	return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI()
468 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)  in CP_LOAD_STATE6_0_DST_OFF()  argument
470 	return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;  in CP_LOAD_STATE6_0_DST_OFF()
474 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)  in CP_LOAD_STATE6_0_STATE_TYPE()  argument
476 	return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;  in CP_LOAD_STATE6_0_STATE_TYPE()
480 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)  in CP_LOAD_STATE6_0_STATE_SRC()  argument
482 	return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;  in CP_LOAD_STATE6_0_STATE_SRC()
486 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)  in CP_LOAD_STATE6_0_STATE_BLOCK()  argument
488 	return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;  in CP_LOAD_STATE6_0_STATE_BLOCK()
492 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)  in CP_LOAD_STATE6_0_NUM_UNIT()  argument
494 	return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;  in CP_LOAD_STATE6_0_NUM_UNIT()
500 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()  argument
502 	return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;  in CP_LOAD_STATE6_1_EXT_SRC_ADDR()
508 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()  argument
510 	return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;  in CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI()
516 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_0_VIZ_QUERY()  argument
518 	return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_0_VIZ_QUERY()
524 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_1_PRIM_TYPE()  argument
526 	return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_1_PRIM_TYPE()
530 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_1_SOURCE_SELECT()  argument
532 	return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_1_SOURCE_SELECT()
536 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_1_VIS_CULL()  argument
538 	return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;  in CP_DRAW_INDX_1_VIS_CULL()
542 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_1_INDEX_SIZE()  argument
544 	return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_1_INDEX_SIZE()
551 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_1_NUM_INSTANCES()  argument
553 	return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_1_NUM_INSTANCES()
559 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_NUM_INDICES()  argument
561 	return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_NUM_INDICES()
567 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_3_INDX_BASE()  argument
569 	return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;  in CP_DRAW_INDX_3_INDX_BASE()
575 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_4_INDX_SIZE()  argument
577 	return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;  in CP_DRAW_INDX_4_INDX_SIZE()
583 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)  in CP_DRAW_INDX_2_0_VIZ_QUERY()  argument
585 	return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;  in CP_DRAW_INDX_2_0_VIZ_QUERY()
591 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_2_1_PRIM_TYPE()  argument
593 	return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;  in CP_DRAW_INDX_2_1_PRIM_TYPE()
597 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_2_1_SOURCE_SELECT()  argument
599 	return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;  in CP_DRAW_INDX_2_1_SOURCE_SELECT()
603 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_2_1_VIS_CULL()  argument
605 	return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;  in CP_DRAW_INDX_2_1_VIS_CULL()
609 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)  in CP_DRAW_INDX_2_1_INDEX_SIZE()  argument
611 	return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;  in CP_DRAW_INDX_2_1_INDEX_SIZE()
618 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_2_1_NUM_INSTANCES()  argument
620 	return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;  in CP_DRAW_INDX_2_1_NUM_INSTANCES()
626 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_2_2_NUM_INDICES()  argument
628 	return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;  in CP_DRAW_INDX_2_2_NUM_INDICES()
634 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()  argument
636 	return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;  in CP_DRAW_INDX_OFFSET_0_PRIM_TYPE()
640 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()  argument
642 …return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT…  in CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT()
646 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()  argument
648 	return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;  in CP_DRAW_INDX_OFFSET_0_VIS_CULL()
652 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()  argument
654 	return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_0_INDEX_SIZE()
658 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)  in CP_DRAW_INDX_OFFSET_0_TESS_MODE()  argument
660 	return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;  in CP_DRAW_INDX_OFFSET_0_TESS_MODE()
666 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()  argument
668 …return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES…  in CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES()
674 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()  argument
676 …return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MA…  in CP_DRAW_INDX_OFFSET_2_NUM_INDICES()
684 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()  argument
686 	return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;  in CP_DRAW_INDX_OFFSET_4_INDX_BASE()
692 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()  argument
694 	return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;  in CP_DRAW_INDX_OFFSET_5_INDX_SIZE()
700 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()  argument
702 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MA…  in A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE()
706 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()  argument
708 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SE…  in A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT()
712 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()  argument
714 	return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;  in A4XX_CP_DRAW_INDIRECT_0_VIS_CULL()
718 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()  argument
720 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__…  in A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE()
724 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)  in A4XX_CP_DRAW_INDIRECT_0_TESS_MODE()  argument
726 …return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MA…  in A4XX_CP_DRAW_INDIRECT_0_TESS_MODE()
732 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()  argument
734 	return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;  in A4XX_CP_DRAW_INDIRECT_1_INDIRECT()
741 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()  argument
743 …return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI…  in A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI()
749 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()  argument
751 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRI…  in A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE()
755 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()  argument
757 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0…  in A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT()
761 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()  argument
763 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_…  in A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL()
767 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()  argument
769 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_IN…  in A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE()
773 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE()  argument
775 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TES…  in A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE()
782 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()  argument
784 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE()
790 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()  argument
792 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_IND…  in A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE()
798 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()  argument
800 …return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDI…  in A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT()
807 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()  argument
809 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_…  in A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO()
815 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()  argument
817 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_…  in A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI()
823 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()  argument
825 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_M…  in A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES()
831 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()  argument
833 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_I…  in A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO()
839 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()  argument
841 …return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_I…  in A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI()
849 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)  in CP_SET_DRAW_STATE__0_COUNT()  argument
851 	return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;  in CP_SET_DRAW_STATE__0_COUNT()
859 static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)  in CP_SET_DRAW_STATE__0_ENABLE_MASK()  argument
861 	return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;  in CP_SET_DRAW_STATE__0_ENABLE_MASK()
865 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)  in CP_SET_DRAW_STATE__0_GROUP_ID()  argument
867 	return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;  in CP_SET_DRAW_STATE__0_GROUP_ID()
873 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)  in CP_SET_DRAW_STATE__1_ADDR_LO()  argument
875 	return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;  in CP_SET_DRAW_STATE__1_ADDR_LO()
881 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)  in CP_SET_DRAW_STATE__2_ADDR_HI()  argument
883 	return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;  in CP_SET_DRAW_STATE__2_ADDR_HI()
891 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)  in CP_SET_BIN_1_X1()  argument
893 	return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;  in CP_SET_BIN_1_X1()
897 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)  in CP_SET_BIN_1_Y1()  argument
899 	return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;  in CP_SET_BIN_1_Y1()
905 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)  in CP_SET_BIN_2_X2()  argument
907 	return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;  in CP_SET_BIN_2_X2()
911 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)  in CP_SET_BIN_2_Y2()  argument
913 	return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;  in CP_SET_BIN_2_Y2()
919 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()  argument
921 	return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;  in CP_SET_BIN_DATA_0_BIN_DATA_ADDR()
927 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()  argument
929 …return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__…  in CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS()
935 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_SIZE()  argument
937 	return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;  in CP_SET_BIN_DATA5_0_VSC_SIZE()
941 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)  in CP_SET_BIN_DATA5_0_VSC_N()  argument
943 	return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;  in CP_SET_BIN_DATA5_0_VSC_N()
949 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()  argument
951 …return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO…  in CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO()
957 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()  argument
959 …return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI…  in CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI()
965 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()  argument
967 …return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO()
973 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()  argument
975 …return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDR…  in CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI()
981 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)  in CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO()  argument
983 …return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_…  in CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO()
989 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)  in CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO()  argument
991 …return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_…  in CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO()
997 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)  in CP_REG_TO_MEM_0_REG()  argument
999 	return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;  in CP_REG_TO_MEM_0_REG()
1003 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)  in CP_REG_TO_MEM_0_CNT()  argument
1005 	return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;  in CP_REG_TO_MEM_0_CNT()
1013 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)  in CP_REG_TO_MEM_1_DEST()  argument
1015 	return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;  in CP_REG_TO_MEM_1_DEST()
1021 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)  in CP_REG_TO_MEM_2_DEST_HI()  argument
1023 	return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;  in CP_REG_TO_MEM_2_DEST_HI()
1029 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)  in CP_MEM_TO_REG_0_REG()  argument
1031 	return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;  in CP_MEM_TO_REG_0_REG()
1035 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)  in CP_MEM_TO_REG_0_CNT()  argument
1037 	return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;  in CP_MEM_TO_REG_0_CNT()
1045 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)  in CP_MEM_TO_REG_1_SRC()  argument
1047 	return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;  in CP_MEM_TO_REG_1_SRC()
1053 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)  in CP_MEM_TO_REG_2_SRC_HI()  argument
1055 	return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;  in CP_MEM_TO_REG_2_SRC_HI()
1067 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE_0_FUNCTION()  argument
1069 	return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;  in CP_COND_WRITE_0_FUNCTION()
1077 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)  in CP_COND_WRITE_1_POLL_ADDR()  argument
1079 	return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;  in CP_COND_WRITE_1_POLL_ADDR()
1085 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)  in CP_COND_WRITE_2_REF()  argument
1087 	return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;  in CP_COND_WRITE_2_REF()
1093 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)  in CP_COND_WRITE_3_MASK()  argument
1095 	return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;  in CP_COND_WRITE_3_MASK()
1101 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)  in CP_COND_WRITE_4_WRITE_ADDR()  argument
1103 	return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;  in CP_COND_WRITE_4_WRITE_ADDR()
1109 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)  in CP_COND_WRITE_5_WRITE_DATA()  argument
1111 	return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;  in CP_COND_WRITE_5_WRITE_DATA()
1117 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)  in CP_COND_WRITE5_0_FUNCTION()  argument
1119 	return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;  in CP_COND_WRITE5_0_FUNCTION()
1127 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_1_POLL_ADDR_LO()  argument
1129 	return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;  in CP_COND_WRITE5_1_POLL_ADDR_LO()
1135 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_2_POLL_ADDR_HI()  argument
1137 	return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;  in CP_COND_WRITE5_2_POLL_ADDR_HI()
1143 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)  in CP_COND_WRITE5_3_REF()  argument
1145 	return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;  in CP_COND_WRITE5_3_REF()
1151 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)  in CP_COND_WRITE5_4_MASK()  argument
1153 	return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;  in CP_COND_WRITE5_4_MASK()
1159 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)  in CP_COND_WRITE5_5_WRITE_ADDR_LO()  argument
1161 	return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;  in CP_COND_WRITE5_5_WRITE_ADDR_LO()
1167 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)  in CP_COND_WRITE5_6_WRITE_ADDR_HI()  argument
1169 	return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;  in CP_COND_WRITE5_6_WRITE_ADDR_HI()
1175 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)  in CP_COND_WRITE5_7_WRITE_DATA()  argument
1177 	return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;  in CP_COND_WRITE5_7_WRITE_DATA()
1185 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)  in CP_DISPATCH_COMPUTE_1_X()  argument
1187 	return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;  in CP_DISPATCH_COMPUTE_1_X()
1193 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)  in CP_DISPATCH_COMPUTE_2_Y()  argument
1195 	return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;  in CP_DISPATCH_COMPUTE_2_Y()
1201 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)  in CP_DISPATCH_COMPUTE_3_Z()  argument
1203 	return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;  in CP_DISPATCH_COMPUTE_3_Z()
1209 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)  in CP_SET_RENDER_MODE_0_MODE()  argument
1211 	return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;  in CP_SET_RENDER_MODE_0_MODE()
1217 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)  in CP_SET_RENDER_MODE_1_ADDR_0_LO()  argument
1219 	return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;  in CP_SET_RENDER_MODE_1_ADDR_0_LO()
1225 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)  in CP_SET_RENDER_MODE_2_ADDR_0_HI()  argument
1227 	return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;  in CP_SET_RENDER_MODE_2_ADDR_0_HI()
1239 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()  argument
1241 	return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;  in CP_SET_RENDER_MODE_5_ADDR_1_LEN()
1247 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)  in CP_SET_RENDER_MODE_6_ADDR_1_LO()  argument
1249 	return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;  in CP_SET_RENDER_MODE_6_ADDR_1_LO()
1255 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)  in CP_SET_RENDER_MODE_7_ADDR_1_HI()  argument
1257 	return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;  in CP_SET_RENDER_MODE_7_ADDR_1_HI()
1263 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()  argument
1265 …return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MA…  in CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO()
1271 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()  argument
1273 …return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MA…  in CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI()
1281 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()  argument
1283 …return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__…  in CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN()
1291 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()  argument
1293 …return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MA…  in CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO()
1299 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()  argument
1301 …return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MA…  in CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI()
1311 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()  argument
1313 …return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MA…  in CP_PERFCOUNTER_ACTION_1_ADDR_0_LO()
1319 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()  argument
1321 …return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MA…  in CP_PERFCOUNTER_ACTION_2_ADDR_0_HI()
1327 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)  in CP_EVENT_WRITE_0_EVENT()  argument
1329 	return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;  in CP_EVENT_WRITE_0_EVENT()
1336 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)  in CP_EVENT_WRITE_1_ADDR_0_LO()  argument
1338 	return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;  in CP_EVENT_WRITE_1_ADDR_0_LO()
1344 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)  in CP_EVENT_WRITE_2_ADDR_0_HI()  argument
1346 	return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;  in CP_EVENT_WRITE_2_ADDR_0_HI()
1354 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)  in CP_BLIT_0_OP()  argument
1356 	return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;  in CP_BLIT_0_OP()
1362 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)  in CP_BLIT_1_SRC_X1()  argument
1364 	return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;  in CP_BLIT_1_SRC_X1()
1368 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)  in CP_BLIT_1_SRC_Y1()  argument
1370 	return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;  in CP_BLIT_1_SRC_Y1()
1376 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)  in CP_BLIT_2_SRC_X2()  argument
1378 	return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;  in CP_BLIT_2_SRC_X2()
1382 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)  in CP_BLIT_2_SRC_Y2()  argument
1384 	return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;  in CP_BLIT_2_SRC_Y2()
1390 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)  in CP_BLIT_3_DST_X1()  argument
1392 	return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;  in CP_BLIT_3_DST_X1()
1396 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)  in CP_BLIT_3_DST_Y1()  argument
1398 	return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;  in CP_BLIT_3_DST_Y1()
1404 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)  in CP_BLIT_4_DST_X2()  argument
1406 	return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;  in CP_BLIT_4_DST_X2()
1410 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)  in CP_BLIT_4_DST_Y2()  argument
1412 	return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;  in CP_BLIT_4_DST_Y2()
1420 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)  in CP_EXEC_CS_1_NGROUPS_X()  argument
1422 	return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;  in CP_EXEC_CS_1_NGROUPS_X()
1428 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)  in CP_EXEC_CS_2_NGROUPS_Y()  argument
1430 	return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;  in CP_EXEC_CS_2_NGROUPS_Y()
1436 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)  in CP_EXEC_CS_3_NGROUPS_Z()  argument
1438 	return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;  in CP_EXEC_CS_3_NGROUPS_Z()
1447 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()  argument
1449 	return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;  in A4XX_CP_EXEC_CS_INDIRECT_1_ADDR()
1455 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()  argument
1457 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX()
1461 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()  argument
1463 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY()
1467 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()  argument
1469 …return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALS…  in A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ()
1476 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()  argument
1478 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__…  in A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO()
1484 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()  argument
1486 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__…  in A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI()
1492 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()  argument
1494 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX()
1498 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()  argument
1500 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY()
1504 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()  argument
1506 …return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALS…  in A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ()
1512 static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)  in A2XX_CP_SET_MARKER_0_MARKER()  argument
1514 	return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;  in A2XX_CP_SET_MARKER_0_MARKER()
1518 static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)  in A2XX_CP_SET_MARKER_0_MODE()  argument
1520 	return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;  in A2XX_CP_SET_MARKER_0_MODE()
1529 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)  in A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()  argument
1531 …return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_R…  in A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG()
1537 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)  in A2XX_CP_SET_PSEUDO_REG__1_LO()  argument
1539 	return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;  in A2XX_CP_SET_PSEUDO_REG__1_LO()
1545 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)  in A2XX_CP_SET_PSEUDO_REG__2_HI()  argument
1547 	return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;  in A2XX_CP_SET_PSEUDO_REG__2_HI()
1553 static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)  in A2XX_CP_REG_TEST_0_REG()  argument
1555 	return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;  in A2XX_CP_REG_TEST_0_REG()
1559 static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)  in A2XX_CP_REG_TEST_0_BIT()  argument
1561 	return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;  in A2XX_CP_REG_TEST_0_BIT()