437 	void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");  in a6xx_gmu_rpmh_init()  local
440 	if (!pdcptr || !seqptr)  in a6xx_gmu_rpmh_init()
474 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);  in a6xx_gmu_rpmh_init()
475 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
476 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);  in a6xx_gmu_rpmh_init()
477 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
478 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
479 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);  in a6xx_gmu_rpmh_init()
480 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
481 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
482 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);  in a6xx_gmu_rpmh_init()
483 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
484 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);  in a6xx_gmu_rpmh_init()
485 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);  in a6xx_gmu_rpmh_init()
486 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);  in a6xx_gmu_rpmh_init()
487 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);  in a6xx_gmu_rpmh_init()
488 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);  in a6xx_gmu_rpmh_init()
489 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);  in a6xx_gmu_rpmh_init()
490 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);  in a6xx_gmu_rpmh_init()
491 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);  in a6xx_gmu_rpmh_init()
492 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);  in a6xx_gmu_rpmh_init()
493 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);  in a6xx_gmu_rpmh_init()
494 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);  in a6xx_gmu_rpmh_init()
495 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);  in a6xx_gmu_rpmh_init()
496 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);  in a6xx_gmu_rpmh_init()
497 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);  in a6xx_gmu_rpmh_init()
500 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);  in a6xx_gmu_rpmh_init()
501 	pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);  in a6xx_gmu_rpmh_init()
507 	if (!IS_ERR_OR_NULL(pdcptr))  in a6xx_gmu_rpmh_init()
508 		iounmap(pdcptr);  in a6xx_gmu_rpmh_init()