46 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit,  in a5xx_submit_in_rb()  argument
50 	struct msm_ringbuffer *ring = submit->ring;  in a5xx_submit_in_rb()
55 	for (i = 0; i < submit->nr_cmds; i++) {  in a5xx_submit_in_rb()
56 		switch (submit->cmd[i].type) {  in a5xx_submit_in_rb()
65 			obj = submit->bos[submit->cmd[i].idx].obj;  in a5xx_submit_in_rb()
66 			dwords = submit->cmd[i].size;  in a5xx_submit_in_rb()
102 	ring->memptrs->fence = submit->seqno;  in a5xx_submit_in_rb()
106 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,  in a5xx_submit()  argument
112 	struct msm_ringbuffer *ring = submit->ring;  in a5xx_submit()
115 	if (IS_ENABLED(CONFIG_DRM_MSM_GPU_SUDO) && submit->in_rb) {  in a5xx_submit()
117 		a5xx_submit_in_rb(gpu, submit, ctx);  in a5xx_submit()
130 	OUT_RING(ring, lower_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
131 	OUT_RING(ring, upper_32_bits(a5xx_gpu->preempt_iova[submit->ring->id]));  in a5xx_submit()
146 	for (i = 0; i < submit->nr_cmds; i++) {  in a5xx_submit()
147 		switch (submit->cmd[i].type) {  in a5xx_submit()
156 			OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));  in a5xx_submit()
157 			OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));  in a5xx_submit()
158 			OUT_RING(ring, submit->cmd[i].size);  in a5xx_submit()
182 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
192 	OUT_RING(ring, submit->seqno);  in a5xx_submit()
1376 		.submit = a5xx_submit,