Lines Matching refs:gpu
17 static void a5xx_dump(struct msm_gpu *gpu);
21 static void a5xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_flush() argument
23 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_flush()
43 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
46 static void a5xx_submit_in_rb(struct msm_gpu *gpu, struct msm_gem_submit *submit, in a5xx_submit_in_rb() argument
49 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit_in_rb()
94 a5xx_flush(gpu, ring); in a5xx_submit_in_rb()
95 a5xx_preempt_trigger(gpu); in a5xx_submit_in_rb()
101 a5xx_idle(gpu, ring); in a5xx_submit_in_rb()
103 msm_gpu_retire(gpu); in a5xx_submit_in_rb()
106 static void a5xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, in a5xx_submit() argument
109 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_submit()
111 struct msm_drm_private *priv = gpu->dev->dev_private; in a5xx_submit()
117 a5xx_submit_in_rb(gpu, submit, ctx); in a5xx_submit()
208 a5xx_flush(gpu, ring); in a5xx_submit()
211 a5xx_preempt_trigger(gpu); in a5xx_submit()
312 void a5xx_set_hwcg(struct msm_gpu *gpu, bool state) in a5xx_set_hwcg() argument
314 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_set_hwcg()
318 gpu_write(gpu, a5xx_hwcg[i].offset, in a5xx_set_hwcg()
322 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); in a5xx_set_hwcg()
323 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0); in a5xx_set_hwcg()
326 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
327 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
330 static int a5xx_me_init(struct msm_gpu *gpu) in a5xx_me_init() argument
332 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_me_init()
333 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_me_init()
364 gpu->funcs->flush(gpu, ring); in a5xx_me_init()
365 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_me_init()
368 static int a5xx_preempt_start(struct msm_gpu *gpu) in a5xx_preempt_start() argument
370 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_preempt_start()
372 struct msm_ringbuffer *ring = gpu->rb[0]; in a5xx_preempt_start()
374 if (gpu->nr_rings == 1) in a5xx_preempt_start()
406 gpu->funcs->flush(gpu, ring); in a5xx_preempt_start()
408 return a5xx_idle(gpu, ring) ? 0 : -EINVAL; in a5xx_preempt_start()
411 static int a5xx_ucode_init(struct msm_gpu *gpu) in a5xx_ucode_init() argument
413 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_ucode_init()
418 a5xx_gpu->pm4_bo = adreno_fw_create_bo(gpu, in a5xx_ucode_init()
425 DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PM4: %d\n", in a5xx_ucode_init()
434 a5xx_gpu->pfp_bo = adreno_fw_create_bo(gpu, in a5xx_ucode_init()
440 DRM_DEV_ERROR(gpu->dev->dev, "could not allocate PFP: %d\n", in a5xx_ucode_init()
448 gpu_write64(gpu, REG_A5XX_CP_ME_INSTR_BASE_LO, in a5xx_ucode_init()
451 gpu_write64(gpu, REG_A5XX_CP_PFP_INSTR_BASE_LO, in a5xx_ucode_init()
459 static int a5xx_zap_shader_resume(struct msm_gpu *gpu) in a5xx_zap_shader_resume() argument
466 gpu->name, ret); in a5xx_zap_shader_resume()
471 static int a5xx_zap_shader_init(struct msm_gpu *gpu) in a5xx_zap_shader_init() argument
481 return a5xx_zap_shader_resume(gpu); in a5xx_zap_shader_init()
483 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID); in a5xx_zap_shader_init()
502 static int a5xx_hw_init(struct msm_gpu *gpu) in a5xx_hw_init() argument
504 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_hw_init()
507 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
510 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a5xx_hw_init()
513 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
516 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
524 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11, in a5xx_hw_init()
526 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12, in a5xx_hw_init()
528 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13, in a5xx_hw_init()
530 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14, in a5xx_hw_init()
532 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15, in a5xx_hw_init()
534 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16, in a5xx_hw_init()
536 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17, in a5xx_hw_init()
538 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18, in a5xx_hw_init()
543 gpu_write(gpu, REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL, in a5xx_hw_init()
547 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); in a5xx_hw_init()
550 gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); in a5xx_hw_init()
553 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0, 6); in a5xx_hw_init()
556 gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02); in a5xx_hw_init()
559 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_LO, 0xFFFF0000); in a5xx_hw_init()
560 gpu_write(gpu, REG_A5XX_UCHE_TRAP_BASE_HI, 0x0001FFFF); in a5xx_hw_init()
561 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_LO, 0xFFFF0000); in a5xx_hw_init()
562 gpu_write(gpu, REG_A5XX_UCHE_WRITE_THRU_BASE_HI, 0x0001FFFF); in a5xx_hw_init()
565 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); in a5xx_hw_init()
566 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); in a5xx_hw_init()
567 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, in a5xx_hw_init()
569 gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); in a5xx_hw_init()
571 gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40); in a5xx_hw_init()
573 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40); in a5xx_hw_init()
575 gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400); in a5xx_hw_init()
576 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060); in a5xx_hw_init()
577 gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16); in a5xx_hw_init()
579 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, (0x400 << 11 | 0x300 << 22)); in a5xx_hw_init()
582 gpu_rmw(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); in a5xx_hw_init()
584 gpu_write(gpu, REG_A5XX_PC_DBG_ECO_CNTL, 0xc0200100); in a5xx_hw_init()
587 gpu_write(gpu, REG_A5XX_CP_CHICKEN_DBG, 0x02000000); in a5xx_hw_init()
590 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL1, 0xA6FFFFFF); in a5xx_hw_init()
593 a5xx_set_hwcg(gpu, true); in a5xx_hw_init()
595 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL2, 0x0000003F); in a5xx_hw_init()
598 gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7); in a5xx_hw_init()
599 gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1); in a5xx_hw_init()
601 gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2); in a5xx_hw_init()
604 gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007); in a5xx_hw_init()
607 gpu_write(gpu, REG_A5XX_CP_PROTECT(0), ADRENO_PROTECT_RW(0x04, 4)); in a5xx_hw_init()
608 gpu_write(gpu, REG_A5XX_CP_PROTECT(1), ADRENO_PROTECT_RW(0x08, 8)); in a5xx_hw_init()
609 gpu_write(gpu, REG_A5XX_CP_PROTECT(2), ADRENO_PROTECT_RW(0x10, 16)); in a5xx_hw_init()
610 gpu_write(gpu, REG_A5XX_CP_PROTECT(3), ADRENO_PROTECT_RW(0x20, 32)); in a5xx_hw_init()
611 gpu_write(gpu, REG_A5XX_CP_PROTECT(4), ADRENO_PROTECT_RW(0x40, 64)); in a5xx_hw_init()
612 gpu_write(gpu, REG_A5XX_CP_PROTECT(5), ADRENO_PROTECT_RW(0x80, 64)); in a5xx_hw_init()
615 gpu_write(gpu, REG_A5XX_CP_PROTECT(6), in a5xx_hw_init()
618 gpu_write(gpu, REG_A5XX_CP_PROTECT(7), in a5xx_hw_init()
622 gpu_write(gpu, REG_A5XX_CP_PROTECT(8), ADRENO_PROTECT_RW(0x800, 64)); in a5xx_hw_init()
623 gpu_write(gpu, REG_A5XX_CP_PROTECT(9), ADRENO_PROTECT_RW(0x840, 8)); in a5xx_hw_init()
624 gpu_write(gpu, REG_A5XX_CP_PROTECT(10), ADRENO_PROTECT_RW(0x880, 32)); in a5xx_hw_init()
625 gpu_write(gpu, REG_A5XX_CP_PROTECT(11), ADRENO_PROTECT_RW(0xAA0, 1)); in a5xx_hw_init()
628 gpu_write(gpu, REG_A5XX_CP_PROTECT(12), ADRENO_PROTECT_RW(0xCC0, 1)); in a5xx_hw_init()
629 gpu_write(gpu, REG_A5XX_CP_PROTECT(13), ADRENO_PROTECT_RW(0xCF0, 2)); in a5xx_hw_init()
632 gpu_write(gpu, REG_A5XX_CP_PROTECT(14), ADRENO_PROTECT_RW(0xE68, 8)); in a5xx_hw_init()
633 gpu_write(gpu, REG_A5XX_CP_PROTECT(15), ADRENO_PROTECT_RW(0xE70, 4)); in a5xx_hw_init()
636 gpu_write(gpu, REG_A5XX_CP_PROTECT(16), ADRENO_PROTECT_RW(0xE80, 16)); in a5xx_hw_init()
639 gpu_write(gpu, REG_A5XX_CP_PROTECT(17), in a5xx_hw_init()
642 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_CNTL, 0); in a5xx_hw_init()
648 gpu_write64(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO, in a5xx_hw_init()
650 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in a5xx_hw_init()
653 gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
654 gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
655 gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
656 gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
657 gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
658 gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
659 gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
660 gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
661 gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
662 gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
663 gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
664 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in a5xx_hw_init()
672 gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23)); in a5xx_hw_init()
673 gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0); in a5xx_hw_init()
676 ret = adreno_hw_init(gpu); in a5xx_hw_init()
680 a5xx_preempt_hw_init(gpu); in a5xx_hw_init()
682 a5xx_gpmu_ucode_init(gpu); in a5xx_hw_init()
684 ret = a5xx_ucode_init(gpu); in a5xx_hw_init()
689 gpu_write(gpu, REG_A5XX_RBBM_INT_0_MASK, A5XX_INT_MASK); in a5xx_hw_init()
692 gpu_write(gpu, REG_A5XX_CP_PFP_ME_CNTL, 0); in a5xx_hw_init()
693 ret = a5xx_me_init(gpu); in a5xx_hw_init()
697 ret = a5xx_power_init(gpu); in a5xx_hw_init()
706 OUT_PKT7(gpu->rb[0], CP_EVENT_WRITE, 1); in a5xx_hw_init()
707 OUT_RING(gpu->rb[0], 0x0F); in a5xx_hw_init()
709 gpu->funcs->flush(gpu, gpu->rb[0]); in a5xx_hw_init()
710 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
721 ret = a5xx_zap_shader_init(gpu); in a5xx_hw_init()
723 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1); in a5xx_hw_init()
724 OUT_RING(gpu->rb[0], 0x00000000); in a5xx_hw_init()
726 gpu->funcs->flush(gpu, gpu->rb[0]); in a5xx_hw_init()
727 if (!a5xx_idle(gpu, gpu->rb[0])) in a5xx_hw_init()
731 dev_warn_once(gpu->dev->dev, in a5xx_hw_init()
733 gpu_write(gpu, REG_A5XX_RBBM_SECVID_TRUST_CNTL, 0x0); in a5xx_hw_init()
737 a5xx_preempt_start(gpu); in a5xx_hw_init()
742 static void a5xx_recover(struct msm_gpu *gpu) in a5xx_recover() argument
746 adreno_dump_info(gpu); in a5xx_recover()
750 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
754 a5xx_dump(gpu); in a5xx_recover()
756 gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1); in a5xx_recover()
757 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
758 gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); in a5xx_recover()
759 adreno_recover(gpu); in a5xx_recover()
762 static void a5xx_destroy(struct msm_gpu *gpu) in a5xx_destroy() argument
764 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_destroy()
767 DBG("%s", gpu->name); in a5xx_destroy()
769 a5xx_preempt_fini(gpu); in a5xx_destroy()
772 msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace); in a5xx_destroy()
777 msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace); in a5xx_destroy()
782 msm_gem_unpin_iova(a5xx_gpu->gpmu_bo, gpu->aspace); in a5xx_destroy()
790 static inline bool _a5xx_check_idle(struct msm_gpu *gpu) in _a5xx_check_idle() argument
792 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
799 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
803 bool a5xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) in a5xx_idle() argument
805 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_idle()
814 if (!adreno_idle(gpu, ring)) in a5xx_idle()
817 if (spin_until(_a5xx_check_idle(gpu))) { in a5xx_idle()
819 gpu->name, __builtin_return_address(0), in a5xx_idle()
820 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
821 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
822 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
823 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
832 struct msm_gpu *gpu = arg; in a5xx_fault_handler() local
835 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
836 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)), in a5xx_fault_handler()
837 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(6)), in a5xx_fault_handler()
838 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(7))); in a5xx_fault_handler()
843 static void a5xx_cp_err_irq(struct msm_gpu *gpu) in a5xx_cp_err_irq() argument
845 u32 status = gpu_read(gpu, REG_A5XX_CP_INTERRUPT_STATUS); in a5xx_cp_err_irq()
850 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, 0); in a5xx_cp_err_irq()
857 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); in a5xx_cp_err_irq()
858 val = gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA); in a5xx_cp_err_irq()
860 dev_err_ratelimited(gpu->dev->dev, "CP | opcode error | possible opcode=0x%8.8X\n", in a5xx_cp_err_irq()
865 dev_err_ratelimited(gpu->dev->dev, "CP | HW fault | status=0x%8.8X\n", in a5xx_cp_err_irq()
866 gpu_read(gpu, REG_A5XX_CP_HW_FAULT)); in a5xx_cp_err_irq()
869 dev_err_ratelimited(gpu->dev->dev, "CP | DMA error\n"); in a5xx_cp_err_irq()
872 u32 val = gpu_read(gpu, REG_A5XX_CP_PROTECT_STATUS); in a5xx_cp_err_irq()
874 dev_err_ratelimited(gpu->dev->dev, in a5xx_cp_err_irq()
881 u32 status = gpu_read(gpu, REG_A5XX_CP_AHB_FAULT); in a5xx_cp_err_irq()
887 dev_err_ratelimited(gpu->dev->dev, in a5xx_cp_err_irq()
894 static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status) in a5xx_rbbm_err_irq() argument
897 u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS); in a5xx_rbbm_err_irq()
899 dev_err_ratelimited(gpu->dev->dev, in a5xx_rbbm_err_irq()
906 gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4)); in a5xx_rbbm_err_irq()
909 gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, in a5xx_rbbm_err_irq()
914 dev_err_ratelimited(gpu->dev->dev, "RBBM | AHB transfer timeout\n"); in a5xx_rbbm_err_irq()
917 dev_err_ratelimited(gpu->dev->dev, "RBBM | ME master split | status=0x%X\n", in a5xx_rbbm_err_irq()
918 gpu_read(gpu, REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
921 dev_err_ratelimited(gpu->dev->dev, "RBBM | PFP master split | status=0x%X\n", in a5xx_rbbm_err_irq()
922 gpu_read(gpu, REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
925 dev_err_ratelimited(gpu->dev->dev, "RBBM | ETS master split | status=0x%X\n", in a5xx_rbbm_err_irq()
926 gpu_read(gpu, REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS)); in a5xx_rbbm_err_irq()
929 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB ASYNC overflow\n"); in a5xx_rbbm_err_irq()
932 dev_err_ratelimited(gpu->dev->dev, "RBBM | ATB bus overflow\n"); in a5xx_rbbm_err_irq()
935 static void a5xx_uche_err_irq(struct msm_gpu *gpu) in a5xx_uche_err_irq() argument
937 uint64_t addr = (uint64_t) gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_HI); in a5xx_uche_err_irq()
939 addr |= gpu_read(gpu, REG_A5XX_UCHE_TRAP_LOG_LO); in a5xx_uche_err_irq()
941 dev_err_ratelimited(gpu->dev->dev, "UCHE | Out of bounds access | addr=0x%llX\n", in a5xx_uche_err_irq()
945 static void a5xx_gpmu_err_irq(struct msm_gpu *gpu) in a5xx_gpmu_err_irq() argument
947 dev_err_ratelimited(gpu->dev->dev, "GPMU | voltage droop\n"); in a5xx_gpmu_err_irq()
950 static void a5xx_fault_detect_irq(struct msm_gpu *gpu) in a5xx_fault_detect_irq() argument
952 struct drm_device *dev = gpu->dev; in a5xx_fault_detect_irq()
954 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu); in a5xx_fault_detect_irq()
958 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_fault_detect_irq()
959 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_fault_detect_irq()
960 gpu_read(gpu, REG_A5XX_CP_RB_WPTR), in a5xx_fault_detect_irq()
961 gpu_read64(gpu, REG_A5XX_CP_IB1_BASE, REG_A5XX_CP_IB1_BASE_HI), in a5xx_fault_detect_irq()
962 gpu_read(gpu, REG_A5XX_CP_IB1_BUFSZ), in a5xx_fault_detect_irq()
963 gpu_read64(gpu, REG_A5XX_CP_IB2_BASE, REG_A5XX_CP_IB2_BASE_HI), in a5xx_fault_detect_irq()
964 gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ)); in a5xx_fault_detect_irq()
967 del_timer(&gpu->hangcheck_timer); in a5xx_fault_detect_irq()
969 queue_work(priv->wq, &gpu->recover_work); in a5xx_fault_detect_irq()
980 static irqreturn_t a5xx_irq(struct msm_gpu *gpu) in a5xx_irq() argument
982 u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS); in a5xx_irq()
988 gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, in a5xx_irq()
993 a5xx_rbbm_err_irq(gpu, status); in a5xx_irq()
996 a5xx_cp_err_irq(gpu); in a5xx_irq()
999 a5xx_fault_detect_irq(gpu); in a5xx_irq()
1002 a5xx_uche_err_irq(gpu); in a5xx_irq()
1005 a5xx_gpmu_err_irq(gpu); in a5xx_irq()
1008 a5xx_preempt_trigger(gpu); in a5xx_irq()
1009 msm_gpu_retire(gpu); in a5xx_irq()
1013 a5xx_preempt_irq(gpu); in a5xx_irq()
1060 static void a5xx_dump(struct msm_gpu *gpu) in a5xx_dump() argument
1062 DRM_DEV_INFO(gpu->dev->dev, "status: %08x\n", in a5xx_dump()
1063 gpu_read(gpu, REG_A5XX_RBBM_STATUS)); in a5xx_dump()
1064 adreno_dump(gpu); in a5xx_dump()
1067 static int a5xx_pm_resume(struct msm_gpu *gpu) in a5xx_pm_resume() argument
1072 ret = msm_gpu_pm_resume(gpu); in a5xx_pm_resume()
1077 gpu_write(gpu, REG_A5XX_GPMU_RBCCU_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1082 ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS, in a5xx_pm_resume()
1086 gpu->name, in a5xx_pm_resume()
1087 gpu_read(gpu, REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS)); in a5xx_pm_resume()
1092 gpu_write(gpu, REG_A5XX_GPMU_SP_POWER_CNTL, 0x778000); in a5xx_pm_resume()
1093 ret = spin_usecs(gpu, 20, REG_A5XX_GPMU_SP_PWR_CLK_STATUS, in a5xx_pm_resume()
1097 gpu->name); in a5xx_pm_resume()
1102 static int a5xx_pm_suspend(struct msm_gpu *gpu) in a5xx_pm_suspend() argument
1105 gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0xF); in a5xx_pm_suspend()
1106 spin_until((gpu_read(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL1) & 0xF) == 0xF); in a5xx_pm_suspend()
1108 gpu_write(gpu, REG_A5XX_VBIF_XIN_HALT_CTRL0, 0); in a5xx_pm_suspend()
1114 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x003C0000); in a5xx_pm_suspend()
1115 gpu_write(gpu, REG_A5XX_RBBM_BLOCK_SW_RESET_CMD, 0x00000000); in a5xx_pm_suspend()
1117 return msm_gpu_pm_suspend(gpu); in a5xx_pm_suspend()
1120 static int a5xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) in a5xx_get_timestamp() argument
1122 *value = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_CP_0_LO, in a5xx_get_timestamp()
1139 static int a5xx_crashdumper_init(struct msm_gpu *gpu, in a5xx_crashdumper_init() argument
1142 dumper->ptr = msm_gem_kernel_new_locked(gpu->dev, in a5xx_crashdumper_init()
1143 SZ_1M, MSM_BO_UNCACHED, gpu->aspace, in a5xx_crashdumper_init()
1152 static int a5xx_crashdumper_run(struct msm_gpu *gpu, in a5xx_crashdumper_run() argument
1160 gpu_write64(gpu, REG_A5XX_CP_CRASH_SCRIPT_BASE_LO, in a5xx_crashdumper_run()
1163 gpu_write(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, 1); in a5xx_crashdumper_run()
1165 return gpu_poll_timeout(gpu, REG_A5XX_CP_CRASH_DUMP_CNTL, val, in a5xx_crashdumper_run()
1196 static void a5xx_gpu_state_get_hlsq_regs(struct msm_gpu *gpu, in a5xx_gpu_state_get_hlsq_regs() argument
1204 if (a5xx_crashdumper_init(gpu, &dumper)) in a5xx_gpu_state_get_hlsq_regs()
1242 if (a5xx_crashdumper_run(gpu, &dumper)) { in a5xx_gpu_state_get_hlsq_regs()
1244 msm_gem_kernel_put(dumper.bo, gpu->aspace, true); in a5xx_gpu_state_get_hlsq_regs()
1252 msm_gem_kernel_put(dumper.bo, gpu->aspace, true); in a5xx_gpu_state_get_hlsq_regs()
1255 static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) in a5xx_gpu_state_get() argument
1264 a5xx_set_hwcg(gpu, false); in a5xx_gpu_state_get()
1267 adreno_gpu_state_get(gpu, &(a5xx_state->base)); in a5xx_gpu_state_get()
1269 a5xx_state->base.rbbm_status = gpu_read(gpu, REG_A5XX_RBBM_STATUS); in a5xx_gpu_state_get()
1272 a5xx_gpu_state_get_hlsq_regs(gpu, a5xx_state); in a5xx_gpu_state_get()
1274 a5xx_set_hwcg(gpu, true); in a5xx_gpu_state_get()
1302 void a5xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, in a5xx_show() argument
1313 adreno_show(gpu, state, p); in a5xx_show()
1343 static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) in a5xx_active_ring() argument
1345 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a5xx_active_ring()
1351 static unsigned long a5xx_gpu_busy(struct msm_gpu *gpu) in a5xx_gpu_busy() argument
1355 busy_cycles = gpu_read64(gpu, REG_A5XX_RBBM_PERFCTR_RBBM_0_LO, in a5xx_gpu_busy()
1358 busy_time = busy_cycles - gpu->devfreq.busy_cycles; in a5xx_gpu_busy()
1359 do_div(busy_time, clk_get_rate(gpu->core_clk) / 1000000); in a5xx_gpu_busy()
1361 gpu->devfreq.busy_cycles = busy_cycles; in a5xx_gpu_busy()
1419 struct msm_gpu *gpu; in a5xx_gpu_init() local
1432 gpu = &adreno_gpu->base; in a5xx_gpu_init()
1447 if (gpu->aspace) in a5xx_gpu_init()
1448 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu, a5xx_fault_handler); in a5xx_gpu_init()
1451 a5xx_preempt_init(gpu); in a5xx_gpu_init()
1453 return gpu; in a5xx_gpu_init()