Lines Matching refs:gpu
32 static void a3xx_dump(struct msm_gpu *gpu);
33 static bool a3xx_idle(struct msm_gpu *gpu);
35 static bool a3xx_me_init(struct msm_gpu *gpu) in a3xx_me_init() argument
37 struct msm_ringbuffer *ring = gpu->rb[0]; in a3xx_me_init()
58 gpu->funcs->flush(gpu, ring); in a3xx_me_init()
59 return a3xx_idle(gpu); in a3xx_me_init()
62 static int a3xx_hw_init(struct msm_gpu *gpu) in a3xx_hw_init() argument
64 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a3xx_hw_init()
69 DBG("%s", gpu->name); in a3xx_hw_init()
73 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
74 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
75 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
76 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
77 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
78 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
79 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
81 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
83 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
85 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
86 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); in a3xx_hw_init()
88 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); in a3xx_hw_init()
89 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a); in a3xx_hw_init()
90 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x0000000a); in a3xx_hw_init()
93 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
94 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
95 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
96 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
97 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
98 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
99 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
101 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
103 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
105 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
106 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); in a3xx_hw_init()
108 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x000000ff); in a3xx_hw_init()
109 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4); in a3xx_hw_init()
118 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f); in a3xx_hw_init()
119 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4); in a3xx_hw_init()
121 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f); in a3xx_hw_init()
122 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
124 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); in a3xx_hw_init()
128 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x18181818); in a3xx_hw_init()
129 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x18181818); in a3xx_hw_init()
130 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x18181818); in a3xx_hw_init()
131 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x18181818); in a3xx_hw_init()
132 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
133 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x18181818); in a3xx_hw_init()
134 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x18181818); in a3xx_hw_init()
136 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x00003f); in a3xx_hw_init()
138 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
140 gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0001); in a3xx_hw_init()
142 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003f); in a3xx_hw_init()
143 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003f003f); in a3xx_hw_init()
145 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT, 0x0001003f); in a3xx_hw_init()
146 gpu_write(gpu, REG_A3XX_VBIF_ABIT_SORT_CONF, 0x000000a4); in a3xx_hw_init()
150 gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001); in a3xx_hw_init()
157 gpu_write(gpu, REG_A3XX_RBBM_GPU_BUSY_MASKED, 0xffffffff); in a3xx_hw_init()
160 gpu_write(gpu, REG_A3XX_RBBM_SP_HYST_CNT, 0x10); in a3xx_hw_init()
161 gpu_write(gpu, REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL, 0x10); in a3xx_hw_init()
166 gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL0, 0x00000001); in a3xx_hw_init()
169 gpu_write(gpu, REG_A3XX_RBBM_AHB_CTL1, 0xa6ffffff); in a3xx_hw_init()
172 gpu_write(gpu, REG_A3XX_RBBM_RBBM_CTL, 0x00030000); in a3xx_hw_init()
177 gpu_write(gpu, REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL, 0x00010fff); in a3xx_hw_init()
180 gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); in a3xx_hw_init()
184 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); in a3xx_hw_init()
186 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); in a3xx_hw_init()
188 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); in a3xx_hw_init()
190 gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbffcffff); in a3xx_hw_init()
193 gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x05515455); in a3xx_hw_init()
195 gpu_write(gpu, REG_A3XX_RBBM_GPR0_CTL, 0x00000000); in a3xx_hw_init()
199 gpu_write(gpu, REG_A3XX_RB_GMEM_BASE_ADDR, in a3xx_hw_init()
204 gpu_write(gpu, REG_A3XX_RBBM_PERFCTR_CTL, 0x01); in a3xx_hw_init()
207 for (i = 0; i < gpu->num_perfcntrs; i++) { in a3xx_hw_init()
208 const struct msm_gpu_perfcntr *perfcntr = &gpu->perfcntrs[i]; in a3xx_hw_init()
209 gpu_write(gpu, perfcntr->select_reg, perfcntr->select_val); in a3xx_hw_init()
212 gpu_write(gpu, REG_A3XX_RBBM_INT_0_MASK, A3XX_INT0_MASK); in a3xx_hw_init()
214 ret = adreno_hw_init(gpu); in a3xx_hw_init()
219 gpu_write(gpu, REG_A3XX_CP_PROTECT_CTRL, 0x00000007); in a3xx_hw_init()
222 gpu_write(gpu, REG_A3XX_CP_PROTECT(0), 0x63000040); in a3xx_hw_init()
223 gpu_write(gpu, REG_A3XX_CP_PROTECT(1), 0x62000080); in a3xx_hw_init()
224 gpu_write(gpu, REG_A3XX_CP_PROTECT(2), 0x600000cc); in a3xx_hw_init()
225 gpu_write(gpu, REG_A3XX_CP_PROTECT(3), 0x60000108); in a3xx_hw_init()
226 gpu_write(gpu, REG_A3XX_CP_PROTECT(4), 0x64000140); in a3xx_hw_init()
227 gpu_write(gpu, REG_A3XX_CP_PROTECT(5), 0x66000400); in a3xx_hw_init()
230 gpu_write(gpu, REG_A3XX_CP_PROTECT(6), 0x65000700); in a3xx_hw_init()
231 gpu_write(gpu, REG_A3XX_CP_PROTECT(7), 0x610007d8); in a3xx_hw_init()
232 gpu_write(gpu, REG_A3XX_CP_PROTECT(8), 0x620007e0); in a3xx_hw_init()
233 gpu_write(gpu, REG_A3XX_CP_PROTECT(9), 0x61001178); in a3xx_hw_init()
234 gpu_write(gpu, REG_A3XX_CP_PROTECT(10), 0x64001180); in a3xx_hw_init()
237 gpu_write(gpu, REG_A3XX_CP_PROTECT(11), 0x60003300); in a3xx_hw_init()
240 gpu_write(gpu, REG_A3XX_CP_PROTECT(12), 0x6b00c000); in a3xx_hw_init()
253 gpu_write(gpu, REG_AXXX_CP_DEBUG, in a3xx_hw_init()
256 gpu_write(gpu, REG_AXXX_CP_ME_RAM_WADDR, 0); in a3xx_hw_init()
258 gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]); in a3xx_hw_init()
265 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0); in a3xx_hw_init()
267 gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_DATA, ptr[i]); in a3xx_hw_init()
272 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, in a3xx_hw_init()
282 gpu_write(gpu, REG_AXXX_CP_QUEUE_THRESHOLDS, 0x003e2008); in a3xx_hw_init()
286 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, 0); in a3xx_hw_init()
288 return a3xx_me_init(gpu) ? 0 : -EINVAL; in a3xx_hw_init()
291 static void a3xx_recover(struct msm_gpu *gpu) in a3xx_recover() argument
295 adreno_dump_info(gpu); in a3xx_recover()
299 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
304 a3xx_dump(gpu); in a3xx_recover()
306 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); in a3xx_recover()
307 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
308 gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0); in a3xx_recover()
309 adreno_recover(gpu); in a3xx_recover()
312 static void a3xx_destroy(struct msm_gpu *gpu) in a3xx_destroy() argument
314 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); in a3xx_destroy()
317 DBG("%s", gpu->name); in a3xx_destroy()
329 static bool a3xx_idle(struct msm_gpu *gpu) in a3xx_idle() argument
332 if (!adreno_idle(gpu, gpu->rb[0])) in a3xx_idle()
336 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
338 DRM_ERROR("%s: timeout waiting for GPU to idle!\n", gpu->name); in a3xx_idle()
347 static irqreturn_t a3xx_irq(struct msm_gpu *gpu) in a3xx_irq() argument
351 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
352 DBG("%s: %08x", gpu->name, status); in a3xx_irq()
356 gpu_write(gpu, REG_A3XX_RBBM_INT_CLEAR_CMD, status); in a3xx_irq()
358 msm_gpu_retire(gpu); in a3xx_irq()
402 static void a3xx_dump(struct msm_gpu *gpu) in a3xx_dump() argument
405 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
406 adreno_dump(gpu); in a3xx_dump()
409 static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) in a3xx_gpu_state_get() argument
416 adreno_gpu_state_get(gpu, state); in a3xx_gpu_state_get()
418 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
465 struct msm_gpu *gpu; in a3xx_gpu_init() local
483 gpu = &adreno_gpu->base; in a3xx_gpu_init()
485 gpu->perfcntrs = perfcntrs; in a3xx_gpu_init()
486 gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs); in a3xx_gpu_init()
510 if (!gpu->aspace) { in a3xx_gpu_init()
523 return gpu; in a3xx_gpu_init()