Lines Matching refs:regmap_write
246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
248 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_venci_cvbs_clock_config()
249 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_venci_cvbs_clock_config()
250 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_venci_cvbs_clock_config()
251 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); in meson_venci_cvbs_clock_config()
252 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
261 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844); in meson_venci_cvbs_clock_config()
262 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c); in meson_venci_cvbs_clock_config()
263 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_venci_cvbs_clock_config()
264 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); in meson_venci_cvbs_clock_config()
276 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); in meson_venci_cvbs_clock_config()
277 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000); in meson_venci_cvbs_clock_config()
278 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); in meson_venci_cvbs_clock_config()
279 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00); in meson_venci_cvbs_clock_config()
280 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290); in meson_venci_cvbs_clock_config()
281 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000); in meson_venci_cvbs_clock_config()
282 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x56540000); in meson_venci_cvbs_clock_config()
283 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7); in meson_venci_cvbs_clock_config()
284 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); in meson_venci_cvbs_clock_config()
459 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m); in meson_hdmi_pll_set_params()
461 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
464 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
466 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); in meson_hdmi_pll_set_params()
467 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); in meson_hdmi_pll_set_params()
468 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); in meson_hdmi_pll_set_params()
469 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); in meson_hdmi_pll_set_params()
480 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m); in meson_hdmi_pll_set_params()
481 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
482 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4); in meson_hdmi_pll_set_params()
483 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000); in meson_hdmi_pll_set_params()
484 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); in meson_hdmi_pll_set_params()
485 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); in meson_hdmi_pll_set_params()
497 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m); in meson_hdmi_pll_set_params()
504 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); in meson_hdmi_pll_set_params()
505 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000); in meson_hdmi_pll_set_params()
510 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, in meson_hdmi_pll_set_params()
512 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, in meson_hdmi_pll_set_params()
515 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, in meson_hdmi_pll_set_params()
517 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, in meson_hdmi_pll_set_params()
520 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000); in meson_hdmi_pll_set_params()
521 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000); in meson_hdmi_pll_set_params()
523 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00); in meson_hdmi_pll_set_params()
524 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290); in meson_hdmi_pll_set_params()
525 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000); in meson_hdmi_pll_set_params()
526 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000); in meson_hdmi_pll_set_params()