Lines Matching refs:regmap_update_bits
140 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
141 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
204 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
208 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
211 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
215 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
219 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
221 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
223 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
226 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
231 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
267 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
269 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
293 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); in meson_venci_cvbs_clock_config()
299 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
304 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
307 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
311 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); in meson_venci_cvbs_clock_config()
314 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_venci_cvbs_clock_config()
317 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
321 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
325 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
329 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
331 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
335 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
338 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
472 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
488 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
490 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
501 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
531 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
535 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
549 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
553 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
556 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
560 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
564 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
567 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
571 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
575 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
578 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
752 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
754 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
756 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
820 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
822 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
829 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
833 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
838 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
842 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
847 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
851 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
856 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
860 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
865 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
869 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
873 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
880 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
885 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
889 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
894 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
899 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
903 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
908 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
913 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
917 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
922 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
927 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
931 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
936 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
941 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
945 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
952 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
956 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
959 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); in meson_vclk_set()