Lines Matching refs:mcde
65 void mcde_display_irq(struct mcde *mcde) in mcde_display_irq() argument
71 mispp = readl(mcde->regs + MCDE_MISPP); in mcde_display_irq()
72 misovl = readl(mcde->regs + MCDE_MISOVL); in mcde_display_irq()
73 mischnl = readl(mcde->regs + MCDE_MISCHNL); in mcde_display_irq()
83 if (mcde_dsi_irq(mcde->mdsi)) { in mcde_display_irq()
92 if (mcde->oneshot_mode) { in mcde_display_irq()
93 spin_lock(&mcde->flow_lock); in mcde_display_irq()
94 if (--mcde->flow_active == 0) { in mcde_display_irq()
95 dev_dbg(mcde->dev, "TE0 IRQ\n"); in mcde_display_irq()
97 val = readl(mcde->regs + MCDE_CRA0); in mcde_display_irq()
99 writel(val, mcde->regs + MCDE_CRA0); in mcde_display_irq()
101 spin_unlock(&mcde->flow_lock); in mcde_display_irq()
107 dev_dbg(mcde->dev, "chnl A vblank IRQ\n"); in mcde_display_irq()
111 dev_dbg(mcde->dev, "chnl B vblank IRQ\n"); in mcde_display_irq()
115 dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n"); in mcde_display_irq()
117 dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n"); in mcde_display_irq()
119 dev_dbg(mcde->dev, "chnl C0 TE IRQ\n"); in mcde_display_irq()
121 dev_dbg(mcde->dev, "chnl C1 TE IRQ\n"); in mcde_display_irq()
122 writel(mispp, mcde->regs + MCDE_RISPP); in mcde_display_irq()
125 drm_crtc_handle_vblank(&mcde->pipe.crtc); in mcde_display_irq()
128 dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl); in mcde_display_irq()
129 writel(misovl, mcde->regs + MCDE_RISOVL); in mcde_display_irq()
132 dev_info(mcde->dev, "some stray channel error IRQ %08x\n", in mcde_display_irq()
134 writel(mischnl, mcde->regs + MCDE_RISCHNL); in mcde_display_irq()
137 void mcde_display_disable_irqs(struct mcde *mcde) in mcde_display_disable_irqs() argument
140 writel(0, mcde->regs + MCDE_IMSCPP); in mcde_display_disable_irqs()
141 writel(0, mcde->regs + MCDE_IMSCOVL); in mcde_display_disable_irqs()
142 writel(0, mcde->regs + MCDE_IMSCCHNL); in mcde_display_disable_irqs()
145 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); in mcde_display_disable_irqs()
146 writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL); in mcde_display_disable_irqs()
147 writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL); in mcde_display_disable_irqs()
187 static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src, in mcde_configure_extsrc() argument
318 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", in mcde_configure_extsrc()
322 writel(val, mcde->regs + conf); in mcde_configure_extsrc()
327 writel(val, mcde->regs + cr); in mcde_configure_extsrc()
332 static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl, in mcde_configure_overlay() argument
401 writel(val, mcde->regs + conf1); in mcde_configure_overlay()
425 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n", in mcde_configure_overlay()
431 writel(val, mcde->regs + conf2); in mcde_configure_overlay()
434 writel(mcde->stride, mcde->regs + ljinc); in mcde_configure_overlay()
436 writel(0, mcde->regs + crop); in mcde_configure_overlay()
448 writel(val, mcde->regs + cr); in mcde_configure_overlay()
455 writel(val, mcde->regs + comp); in mcde_configure_overlay()
458 static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch, in mcde_configure_channel() argument
501 if (mcde->te_sync) { in mcde_configure_channel()
519 writel(val, mcde->regs + sync); in mcde_configure_channel()
524 writel(val, mcde->regs + conf); in mcde_configure_channel()
532 writel(val, mcde->regs + stat); in mcde_configure_channel()
533 writel(0, mcde->regs + bgcol); in mcde_configure_channel()
539 mcde->regs + mux); in mcde_configure_channel()
543 mcde->regs + mux); in mcde_configure_channel()
548 static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo, in mcde_configure_fifo() argument
576 writel(val, mcde->regs + ctrl); in mcde_configure_fifo()
581 writel(val, mcde->regs + cr0); in mcde_configure_fifo()
589 writel(val, mcde->regs + cr1); in mcde_configure_fifo()
592 static void mcde_configure_dsi_formatter(struct mcde *mcde, in mcde_configure_dsi_formatter() argument
640 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) in mcde_configure_dsi_formatter()
642 switch (mcde->mdsi->format) { in mcde_configure_dsi_formatter()
660 dev_err(mcde->dev, "unknown DSI format\n"); in mcde_configure_dsi_formatter()
663 writel(val, mcde->regs + conf0); in mcde_configure_dsi_formatter()
665 writel(formatter_frame, mcde->regs + frame); in mcde_configure_dsi_formatter()
666 writel(pkt_size, mcde->regs + pkt); in mcde_configure_dsi_formatter()
667 writel(0, mcde->regs + sync); in mcde_configure_dsi_formatter()
673 writel(val, mcde->regs + cmdw); in mcde_configure_dsi_formatter()
679 writel(0, mcde->regs + delay0); in mcde_configure_dsi_formatter()
680 writel(0, mcde->regs + delay1); in mcde_configure_dsi_formatter()
683 static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo) in mcde_enable_fifo() argument
696 dev_err(mcde->dev, "cannot enable FIFO %c\n", in mcde_enable_fifo()
701 spin_lock(&mcde->flow_lock); in mcde_enable_fifo()
702 val = readl(mcde->regs + cr); in mcde_enable_fifo()
704 writel(val, mcde->regs + cr); in mcde_enable_fifo()
705 mcde->flow_active++; in mcde_enable_fifo()
706 spin_unlock(&mcde->flow_lock); in mcde_enable_fifo()
709 static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo, in mcde_disable_fifo() argument
724 dev_err(mcde->dev, "cannot disable FIFO %c\n", in mcde_disable_fifo()
729 spin_lock(&mcde->flow_lock); in mcde_disable_fifo()
730 val = readl(mcde->regs + cr); in mcde_disable_fifo()
732 writel(val, mcde->regs + cr); in mcde_disable_fifo()
733 mcde->flow_active = 0; in mcde_disable_fifo()
734 spin_unlock(&mcde->flow_lock); in mcde_disable_fifo()
740 while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) { in mcde_disable_fifo()
743 dev_err(mcde->dev, in mcde_disable_fifo()
754 static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo, in mcde_drain_pipe() argument
785 val = readl(mcde->regs + ctrl); in mcde_drain_pipe()
787 dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n"); in mcde_drain_pipe()
789 mcde_enable_fifo(mcde, fifo); in mcde_drain_pipe()
791 writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw); in mcde_drain_pipe()
793 mcde_disable_fifo(mcde, fifo, true); in mcde_drain_pipe()
819 struct mcde *mcde = drm->dev_private; in mcde_display_enable() local
836 if (!mcde->mdsi) { in mcde_display_enable()
843 (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ? in mcde_display_enable()
845 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format)); in mcde_display_enable()
847 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8; in mcde_display_enable()
864 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in mcde_display_enable()
879 if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in mcde_display_enable()
886 mcde->stride = mode->hdisplay * cpp; in mcde_display_enable()
888 mcde->stride); in mcde_display_enable()
894 mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0); in mcde_display_enable()
903 mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format); in mcde_display_enable()
910 mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0, in mcde_display_enable()
917 mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode); in mcde_display_enable()
920 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0, in mcde_display_enable()
924 mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0, in mcde_display_enable()
927 if (mcde->te_sync) { in mcde_display_enable()
932 writel(val, mcde->regs + MCDE_VSCRC0); in mcde_display_enable()
934 val = readl(mcde->regs + MCDE_CRC); in mcde_display_enable()
936 writel(val, mcde->regs + MCDE_CRC); in mcde_display_enable()
948 struct mcde *mcde = drm->dev_private; in mcde_display_disable() local
950 if (mcde->te_sync) in mcde_display_disable()
954 mcde_disable_fifo(mcde, MCDE_FIFO_A, true); in mcde_display_disable()
959 static void mcde_display_send_one_frame(struct mcde *mcde) in mcde_display_send_one_frame() argument
962 if (mcde->te_sync) in mcde_display_send_one_frame()
963 mcde_dsi_te_request(mcde->mdsi); in mcde_display_send_one_frame()
966 mcde_enable_fifo(mcde, MCDE_FIFO_A); in mcde_display_send_one_frame()
968 if (mcde->te_sync) { in mcde_display_send_one_frame()
975 dev_dbg(mcde->dev, "sent TE0 framebuffer update\n"); in mcde_display_send_one_frame()
981 mcde->regs + MCDE_CHNL0SYNCHSW); in mcde_display_send_one_frame()
990 mcde_disable_fifo(mcde, MCDE_FIFO_A, true); in mcde_display_send_one_frame()
992 dev_dbg(mcde->dev, "sent SW framebuffer update\n"); in mcde_display_send_one_frame()
995 static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address) in mcde_set_extsrc() argument
998 writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0); in mcde_set_extsrc()
1003 writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1); in mcde_set_extsrc()
1011 struct mcde *mcde = drm->dev_private; in mcde_display_update() local
1034 dev_dbg(mcde->dev, "arm vblank event\n"); in mcde_display_update()
1037 dev_dbg(mcde->dev, "insert fake vblank event\n"); in mcde_display_update()
1050 mcde_set_extsrc(mcde, drm_fb_cma_get_gem_addr(fb, pstate, 0)); in mcde_display_update()
1052 mcde_display_send_one_frame(mcde); in mcde_display_update()
1053 dev_info_once(mcde->dev, "sent first display update\n"); in mcde_display_update()
1060 dev_info(mcde->dev, "ignored a display update\n"); in mcde_display_update()
1068 struct mcde *mcde = drm->dev_private; in mcde_display_enable_vblank() local
1078 writel(val, mcde->regs + MCDE_IMSCPP); in mcde_display_enable_vblank()
1087 struct mcde *mcde = drm->dev_private; in mcde_display_disable_vblank() local
1090 writel(0, mcde->regs + MCDE_IMSCPP); in mcde_display_disable_vblank()
1092 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP); in mcde_display_disable_vblank()
1105 struct mcde *mcde = drm->dev_private; in mcde_display_init() local
1127 if (mcde->te_sync) { in mcde_display_init()
1132 ret = drm_simple_display_pipe_init(drm, &mcde->pipe, in mcde_display_init()
1136 mcde->connector); in mcde_display_init()