192 	u32 cr;  in mcde_configure_extsrc()  local
197 		cr = MCDE_EXTSRC0CR;  in mcde_configure_extsrc()
201 		cr = MCDE_EXTSRC1CR;  in mcde_configure_extsrc()
205 		cr = MCDE_EXTSRC2CR;  in mcde_configure_extsrc()
209 		cr = MCDE_EXTSRC3CR;  in mcde_configure_extsrc()
213 		cr = MCDE_EXTSRC4CR;  in mcde_configure_extsrc()
217 		cr = MCDE_EXTSRC5CR;  in mcde_configure_extsrc()
221 		cr = MCDE_EXTSRC6CR;  in mcde_configure_extsrc()
225 		cr = MCDE_EXTSRC7CR;  in mcde_configure_extsrc()
229 		cr = MCDE_EXTSRC8CR;  in mcde_configure_extsrc()
233 		cr = MCDE_EXTSRC9CR;  in mcde_configure_extsrc()
327 	writel(val, mcde->regs + cr);  in mcde_configure_extsrc()
343 	u32 cr;  in mcde_configure_overlay()  local
352 		cr = MCDE_OVL0CR;  in mcde_configure_overlay()
360 		cr = MCDE_OVL1CR;  in mcde_configure_overlay()
368 		cr = MCDE_OVL2CR;  in mcde_configure_overlay()
376 		cr = MCDE_OVL3CR;  in mcde_configure_overlay()
384 		cr = MCDE_OVL4CR;  in mcde_configure_overlay()
392 		cr = MCDE_OVL5CR;  in mcde_configure_overlay()
448 	writel(val, mcde->regs + cr);  in mcde_configure_overlay()
686 	u32 cr;  in mcde_enable_fifo()  local
690 		cr = MCDE_CRA0;  in mcde_enable_fifo()
693 		cr = MCDE_CRB0;  in mcde_enable_fifo()
702 	val = readl(mcde->regs + cr);  in mcde_enable_fifo()
704 	writel(val, mcde->regs + cr);  in mcde_enable_fifo()
714 	u32 cr;  in mcde_disable_fifo()  local
718 		cr = MCDE_CRA0;  in mcde_disable_fifo()
721 		cr = MCDE_CRB0;  in mcde_disable_fifo()
730 	val = readl(mcde->regs + cr);  in mcde_disable_fifo()
732 	writel(val, mcde->regs + cr);  in mcde_disable_fifo()
740 	while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {  in mcde_disable_fifo()