6408 	u16 rgvswctl;  in ironlake_set_drps()  local
6412 	rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);  in ironlake_set_drps()
6413 	if (rgvswctl & MEMCTL_CMD_STS) {  in ironlake_set_drps()
6418 	rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |  in ironlake_set_drps()
6420 	intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);  in ironlake_set_drps()
6423 	rgvswctl |= MEMCTL_CMD_STS;  in ironlake_set_drps()
6424 	intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);  in ironlake_set_drps()
6507 	u16 rgvswctl;  in ironlake_disable_drps()  local
6511 	rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);  in ironlake_disable_drps()
6530 	rgvswctl |= MEMCTL_CMD_STS;  in ironlake_disable_drps()
6531 	intel_uncore_write(uncore, MEMSWCTL, rgvswctl);  in ironlake_disable_drps()