3090 				 struct intel_pipe_wm *pipe_wm)  in ilk_validate_pipe_wm()  argument
3095 		.sprites_enabled = pipe_wm->sprites_enabled,  in ilk_validate_pipe_wm()
3096 		.sprites_scaled = pipe_wm->sprites_scaled,  in ilk_validate_pipe_wm()
3104 	if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {  in ilk_validate_pipe_wm()
3117 	struct intel_pipe_wm *pipe_wm;  in ilk_compute_pipe_wm()  local
3128 	pipe_wm = &crtc_state->wm.ilk.optimal;  in ilk_compute_pipe_wm()
3141 	pipe_wm->pipe_enabled = crtc_state->base.active;  in ilk_compute_pipe_wm()
3143 		pipe_wm->sprites_enabled = sprstate->base.visible;  in ilk_compute_pipe_wm()
3144 		pipe_wm->sprites_scaled = sprstate->base.visible &&  in ilk_compute_pipe_wm()
3152 	if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)  in ilk_compute_pipe_wm()
3156 	if (pipe_wm->sprites_scaled)  in ilk_compute_pipe_wm()
3159 	memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));  in ilk_compute_pipe_wm()
3161 			     pristate, sprstate, curstate, &pipe_wm->wm[0]);  in ilk_compute_pipe_wm()
3164 		pipe_wm->linetime = hsw_compute_linetime_wm(crtc_state);  in ilk_compute_pipe_wm()
3166 	if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))  in ilk_compute_pipe_wm()
3172 		struct intel_wm_level *wm = &pipe_wm->wm[level];  in ilk_compute_pipe_wm()
3343 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)  in ilk_wm_lp_to_level()  argument
3346 	return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);  in ilk_wm_lp_to_level()
5092 	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_build_pipe_wm()  local
5101 	memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));  in skl_build_pipe_wm()
5116 	pipe_wm->linetime = skl_compute_linetime_wm(crtc_state);  in skl_build_pipe_wm()
5653 	struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;  in skl_atomic_update_crtc_wm()  local
5659 	I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);  in skl_atomic_update_crtc_wm()