820 	return dev_priv->wm.max_level + 1;  in intel_wm_num_levels()
1066 	dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;  in g4x_setup_wm_latency()
1298 	if (level > dev_priv->wm.max_level)  in g4x_raw_crtc_wm_is_valid()
1610 	dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;  in vlv_setup_wm_latency()
1616 		dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;  in vlv_setup_wm_latency()
2111 	wm->level = dev_priv->wm.max_level;  in vlv_merge_wm()
2832 		int level, max_level = ilk_wm_max_level(dev_priv);  in intel_read_wm_latency()  local
2876 		for (level = 1; level <= max_level; level++) {  in intel_read_wm_latency()
2878 				for (i = level + 1; i <= max_level; i++)  in intel_read_wm_latency()
2893 			for (level = 1; level <= max_level; level++) {  in intel_read_wm_latency()
2971 	int level, max_level = ilk_wm_max_level(dev_priv);  in intel_print_wm_latency()  local
2973 	for (level = 0; level <= max_level; level++) {  in intel_print_wm_latency()
3000 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_increase_wm_latency()  local
3006 	for (level = 1; level <= max_level; level++)  in ilk_increase_wm_latency()
3125 	int level, max_level = ilk_wm_max_level(dev_priv), usable_level;  in ilk_compute_pipe_wm()  local
3149 	usable_level = max_level;  in ilk_compute_pipe_wm()
3206 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_compute_intermediate_wm()  local
3222 	for (level = 0; level <= max_level; level++) {  in ilk_compute_intermediate_wm()
3293 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_wm_merge()  local
3294 	int last_enabled_level = max_level;  in ilk_wm_merge()
3305 	for (level = 1; level <= max_level; level++) {  in ilk_wm_merge()
3335 		for (level = 2; level <= max_level; level++) {  in ilk_wm_merge()
3433 	int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_find_best_result()  local
3436 	for (level = 1; level <= max_level; level++) {  in ilk_find_best_result()
3950 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_cursor_allocation()  local
3962 	for (level = 0; level <= max_level; level++) {  in skl_cursor_allocation()
4896 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_compute_wm_levels()  local
4899 	for (level = 0; level <= max_level; level++) {  in skl_compute_wm_levels()
5151 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_write_plane_wm()  local
5161 	for (level = 0; level <= max_level; level++) {  in skl_write_plane_wm()
5187 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_write_cursor_wm()  local
5195 	for (level = 0; level <= max_level; level++) {  in skl_write_cursor_wm()
5217 	int level, max_level = ilk_wm_max_level(dev_priv);  in skl_plane_wm_equals()  local
5219 	for (level = 0; level <= max_level; level++) {  in skl_plane_wm_equals()
5773 	int level, max_level;  in skl_pipe_wm_get_hw_state()  local
5777 	max_level = ilk_wm_max_level(dev_priv);  in skl_pipe_wm_get_hw_state()
5782 		for (level = 0; level <= max_level; level++) {  in skl_pipe_wm_get_hw_state()
5865 		int level, max_level = ilk_wm_max_level(dev_priv);  in ilk_pipe_wm_get_hw_state()  local
5872 		for (level = 0; level <= max_level; level++)  in ilk_pipe_wm_get_hw_state()
6002 		int level, max_level;  in g4x_wm_get_hw_state()  local
6017 			max_level = G4X_WM_LEVEL_HPLL;  in g4x_wm_get_hw_state()
6019 			max_level = G4X_WM_LEVEL_SR;  in g4x_wm_get_hw_state()
6021 			max_level = G4X_WM_LEVEL_NORMAL;  in g4x_wm_get_hw_state()
6028 		if (++level > max_level)  in g4x_wm_get_hw_state()
6037 		if (++level > max_level)  in g4x_wm_get_hw_state()
6161 			dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;  in vlv_wm_get_hw_state()