227 	dev_priv->ips.r_t = dev_priv->mem_freq;  in i915_ironlake_get_mem_freq()
259 		dev_priv->ips.c_m = 0;  in i915_ironlake_get_mem_freq()
261 		dev_priv->ips.c_m = 1;  in i915_ironlake_get_mem_freq()
263 		dev_priv->ips.c_m = 2;  in i915_ironlake_get_mem_freq()
6462 	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */  in ironlake_enable_drps()
6463 	dev_priv->ips.fstart = fstart;  in ironlake_enable_drps()
6465 	dev_priv->ips.max_delay = fstart;  in ironlake_enable_drps()
6466 	dev_priv->ips.min_delay = fmin;  in ironlake_enable_drps()
6467 	dev_priv->ips.cur_delay = fstart;  in ironlake_enable_drps()
6493 	dev_priv->ips.last_count1 =  in ironlake_enable_drps()
6497 	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);  in ironlake_enable_drps()
6498 	dev_priv->ips.last_count2 = intel_uncore_read(uncore, GFXEC);  in ironlake_enable_drps()
6499 	dev_priv->ips.last_time2 = ktime_get_raw_ns();  in ironlake_enable_drps()
6528 	ironlake_set_drps(i915, i915->ips.fstart);  in ironlake_disable_drps()
8114 	diff1 = now - dev_priv->ips.last_time1;  in __i915_chipset_val()
8122 		return dev_priv->ips.chipset_power;  in __i915_chipset_val()
8131 	if (total_count < dev_priv->ips.last_count1) {  in __i915_chipset_val()
8132 		diff = ~0UL - dev_priv->ips.last_count1;  in __i915_chipset_val()
8135 		diff = total_count - dev_priv->ips.last_count1;  in __i915_chipset_val()
8139 		if (cparams[i].i == dev_priv->ips.c_m &&  in __i915_chipset_val()
8140 		    cparams[i].t == dev_priv->ips.r_t) {  in __i915_chipset_val()
8151 	dev_priv->ips.last_count1 = total_count;  in __i915_chipset_val()
8152 	dev_priv->ips.last_time1 = now;  in __i915_chipset_val()
8154 	dev_priv->ips.chipset_power = ret;  in __i915_chipset_val()
8221 	diffms = now - dev_priv->ips.last_time2;  in __i915_update_gfx_val()
8230 	if (count < dev_priv->ips.last_count2) {  in __i915_update_gfx_val()
8231 		diff = ~0UL - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
8234 		diff = count - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
8237 	dev_priv->ips.last_count2 = count;  in __i915_update_gfx_val()
8238 	dev_priv->ips.last_time2 = now;  in __i915_update_gfx_val()
8243 	dev_priv->ips.gfx_power = diff;  in __i915_update_gfx_val()
8287 	corr2 = (corr * dev_priv->ips.corr);  in __i915_gfx_val()
8294 	return dev_priv->ips.gfx_power + state2;  in __i915_gfx_val()
8372 	if (i915->ips.max_delay > i915->ips.fmax)  in i915_gpu_raise()
8373 		i915->ips.max_delay--;  in i915_gpu_raise()
8396 	if (i915->ips.max_delay < i915->ips.min_delay)  in i915_gpu_lower()
8397 		i915->ips.max_delay++;  in i915_gpu_lower()
8442 	i915->ips.max_delay = i915->ips.fstart;  in i915_gpu_turbo_disable()
8443 	ret = ironlake_set_drps(i915, i915->ips.fstart);  in i915_gpu_turbo_disable()
8552 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);  in intel_init_emon()