468 		dev_priv->wm.g4x.cxsr = enable;  in intel_set_memory_cxsr()
1182 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_set()
1201 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_fbc_wm_set()
1231 		struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_compute()
1272 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],  in g4x_raw_plane_wm_compute()
1273 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],  in g4x_raw_plane_wm_compute()
1274 			      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);  in g4x_raw_plane_wm_compute()
1278 				      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,  in g4x_raw_plane_wm_compute()
1279 				      crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);  in g4x_raw_plane_wm_compute()
1288 	const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];  in g4x_raw_plane_wm_is_valid()
1337 	struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_compute_pipe_wm()
1366 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1375 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1387 	raw = &crtc_state->wm.g4x.raw[level];  in g4x_compute_pipe_wm()
1424 	struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;  in g4x_compute_intermediate_wm()
1425 	const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1430 	const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;  in g4x_compute_intermediate_wm()
1508 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1530 		const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;  in g4x_merge_wm()
1543 	struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;  in g4x_program_watermarks()
1569 	crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;  in g4x_initial_watermarks()
1584 	crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_optimize_watermarks()
5988 	struct g4x_wm_values *wm = &dev_priv->wm.g4x;  in g4x_wm_get_hw_state()
5998 		struct g4x_wm_state *active = &crtc->wm.active.g4x;  in g4x_wm_get_hw_state()
6024 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6031 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6040 		raw = &crtc_state->wm.g4x.raw[level];  in g4x_wm_get_hw_state()
6052 		crtc_state->wm.g4x.optimal = *active;  in g4x_wm_get_hw_state()
6053 		crtc_state->wm.g4x.intermediate = *active;  in g4x_wm_get_hw_state()
6084 		struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6093 				&crtc_state->wm.g4x.raw[level];  in g4x_wm_sanitize()
6102 					&crtc_state->wm.g4x.raw[level];  in g4x_wm_sanitize()
6116 		crtc_state->wm.g4x.intermediate =  in g4x_wm_sanitize()
6117 			crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()
6118 		crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;  in g4x_wm_sanitize()