297 	u32 *payload = dev_priv->csr.dmc_payload;  in intel_csr_load_program()
305 	if (!dev_priv->csr.dmc_payload) {  in intel_csr_load_program()
310 	fw_size = dev_priv->csr.dmc_fw_size;  in intel_csr_load_program()
320 	for (i = 0; i < dev_priv->csr.mmio_count; i++) {  in intel_csr_load_program()
321 		I915_WRITE(dev_priv->csr.mmioaddr[i],  in intel_csr_load_program()
322 			   dev_priv->csr.mmiodata[i]);  in intel_csr_load_program()
325 	dev_priv->csr.dc_state = 0;  in intel_csr_load_program()
374 static u32 parse_csr_fw_dmc(struct intel_csr *csr,  in parse_csr_fw_dmc()  argument
383 	BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||  in parse_csr_fw_dmc()
384 		     ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);  in parse_csr_fw_dmc()
446 		csr->mmioaddr[i] = _MMIO(mmioaddr[i]);  in parse_csr_fw_dmc()
447 		csr->mmiodata[i] = mmiodata[i];  in parse_csr_fw_dmc()
449 	csr->mmio_count = mmio_count;  in parse_csr_fw_dmc()
458 	if (payload_size > csr->max_fw_size) {  in parse_csr_fw_dmc()
462 	csr->dmc_fw_size = dmc_header->fw_size;  in parse_csr_fw_dmc()
464 	csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);  in parse_csr_fw_dmc()
465 	if (!csr->dmc_payload) {  in parse_csr_fw_dmc()
471 	memcpy(csr->dmc_payload, payload, payload_size);  in parse_csr_fw_dmc()
481 parse_csr_fw_package(struct intel_csr *csr,  in parse_csr_fw_package()  argument
540 static u32 parse_csr_fw_css(struct intel_csr *csr,  in parse_csr_fw_css()  argument
557 	if (csr->required_version &&  in parse_csr_fw_css()
558 	    css_header->version != csr->required_version) {  in parse_csr_fw_css()
563 			 CSR_VERSION_MAJOR(csr->required_version),  in parse_csr_fw_css()
564 			 CSR_VERSION_MINOR(csr->required_version));  in parse_csr_fw_css()
568 	csr->version = css_header->version;  in parse_csr_fw_css()
579 	struct intel_csr *csr = &dev_priv->csr;  in parse_csr_fw()  local
589 	r = parse_csr_fw_css(csr, css_header, fw->size);  in parse_csr_fw()
597 	r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);  in parse_csr_fw()
605 	parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);  in parse_csr_fw()
610 	WARN_ON(dev_priv->csr.wakeref);  in intel_csr_runtime_pm_get()
611 	dev_priv->csr.wakeref =  in intel_csr_runtime_pm_get()
618 		fetch_and_zero(&dev_priv->csr.wakeref);  in intel_csr_runtime_pm_put()
626 	struct intel_csr *csr;  in csr_load_work_fn()  local
629 	dev_priv = container_of(work, typeof(*dev_priv), csr.work);  in csr_load_work_fn()
630 	csr = &dev_priv->csr;  in csr_load_work_fn()
632 	request_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);  in csr_load_work_fn()
635 	if (dev_priv->csr.dmc_payload) {  in csr_load_work_fn()
640 			 dev_priv->csr.fw_path,  in csr_load_work_fn()
641 			 CSR_VERSION_MAJOR(csr->version),  in csr_load_work_fn()
642 			 CSR_VERSION_MINOR(csr->version));  in csr_load_work_fn()
647 			   csr->fw_path);  in csr_load_work_fn()
664 	struct intel_csr *csr = &dev_priv->csr;  in intel_csr_ucode_init()  local
666 	INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);  in intel_csr_ucode_init()
682 		csr->fw_path = TGL_CSR_PATH;  in intel_csr_ucode_init()
683 		csr->required_version = TGL_CSR_VERSION_REQUIRED;  in intel_csr_ucode_init()
685 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;  in intel_csr_ucode_init()
687 		csr->fw_path = ICL_CSR_PATH;  in intel_csr_ucode_init()
688 		csr->required_version = ICL_CSR_VERSION_REQUIRED;  in intel_csr_ucode_init()
689 		csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;  in intel_csr_ucode_init()
691 		csr->fw_path = CNL_CSR_PATH;  in intel_csr_ucode_init()
692 		csr->required_version = CNL_CSR_VERSION_REQUIRED;  in intel_csr_ucode_init()
693 		csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;  in intel_csr_ucode_init()
695 		csr->fw_path = GLK_CSR_PATH;  in intel_csr_ucode_init()
696 		csr->required_version = GLK_CSR_VERSION_REQUIRED;  in intel_csr_ucode_init()
697 		csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;  in intel_csr_ucode_init()
699 		csr->fw_path = KBL_CSR_PATH;  in intel_csr_ucode_init()
700 		csr->required_version = KBL_CSR_VERSION_REQUIRED;  in intel_csr_ucode_init()
701 		csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;  in intel_csr_ucode_init()
703 		csr->fw_path = SKL_CSR_PATH;  in intel_csr_ucode_init()
704 		csr->required_version = SKL_CSR_VERSION_REQUIRED;  in intel_csr_ucode_init()
705 		csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;  in intel_csr_ucode_init()
707 		csr->fw_path = BXT_CSR_PATH;  in intel_csr_ucode_init()
708 		csr->required_version = BXT_CSR_VERSION_REQUIRED;  in intel_csr_ucode_init()
709 		csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;  in intel_csr_ucode_init()
714 			csr->fw_path = NULL;  in intel_csr_ucode_init()
719 		csr->fw_path = i915_modparams.dmc_firmware_path;  in intel_csr_ucode_init()
721 		csr->required_version = 0;  in intel_csr_ucode_init()
724 	if (csr->fw_path == NULL) {  in intel_csr_ucode_init()
729 	DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);  in intel_csr_ucode_init()
730 	schedule_work(&dev_priv->csr.work);  in intel_csr_ucode_init()
746 	flush_work(&dev_priv->csr.work);  in intel_csr_ucode_suspend()
749 	if (!dev_priv->csr.dmc_payload)  in intel_csr_ucode_suspend()
769 	if (!dev_priv->csr.dmc_payload)  in intel_csr_ucode_resume()
786 	WARN_ON(dev_priv->csr.wakeref);  in intel_csr_ucode_fini()
788 	kfree(dev_priv->csr.dmc_payload);  in intel_csr_ucode_fini()