Lines Matching refs:VLV_DISPLAY_BASE
204 #define VLV_DISPLAY_BASE 0x180000 macro
205 #define VLV_MIPI_BASE VLV_DISPLAY_BASE
1067 #define VLV_IOSF_DOORBELL_REQ _MMIO(VLV_DISPLAY_BASE + 0x2100)
1089 #define VLV_IOSF_DATA _MMIO(VLV_DISPLAY_BASE + 0x2104)
1090 #define VLV_IOSF_ADDR _MMIO(VLV_DISPLAY_BASE + 0x2108)
1266 #define DPIO_CTL _MMIO(VLV_DISPLAY_BASE + 0x2110)
2608 #define CLAIM_ER _MMIO(VLV_DISPLAY_BASE + 0x2028)
2711 #define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
2712 #define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
2718 #define VLV_GUNIT_CLOCK_GATE _MMIO(VLV_DISPLAY_BASE + 0x2060)
2721 #define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
2722 #define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
2723 #define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
2724 #define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
2725 #define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
2726 #define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
2727 #define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
2904 #define CHV_FUSE_GT _MMIO(VLV_DISPLAY_BASE + 0x2168)
3042 #define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000)
3046 #define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38)
3049 #define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20)
3050 #define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30)
3051 #define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34)
3297 #define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
3299 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
3310 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
3395 #define RAWCLK_FREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6024)
3542 #define FW_BLC_SELF_VLV _MMIO(VLV_DISPLAY_BASE + 0x6500)
3545 #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
3547 #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
3552 #define GCI_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x650C)
3559 #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
4337 #define VLV_ADPA _MMIO(VLV_DISPLAY_BASE + 0x61100)
4486 #define VLV_HDMIB _MMIO(VLV_DISPLAY_BASE + 0x61140)
4487 #define VLV_HDMIC _MMIO(VLV_DISPLAY_BASE + 0x61160)
4488 #define CHV_HDMID _MMIO(VLV_DISPLAY_BASE + 0x6116C)
4695 #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE)
5397 #define VLV_DP_B _MMIO(VLV_DISPLAY_BASE + 0x64100)
5398 #define VLV_DP_C _MMIO(VLV_DISPLAY_BASE + 0x64200)
5399 #define CHV_DP_D _MMIO(VLV_DISPLAY_BASE + 0x64300)
5772 #define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
5793 #define DPINVGTT _MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
5838 #define DSPARB2 _MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
5851 #define DSPARB3 _MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
5896 #define DSPFW4 _MMIO(VLV_DISPLAY_BASE + 0x70070)
5903 #define DSPFW5 _MMIO(VLV_DISPLAY_BASE + 0x70074)
5912 #define DSPFW6 _MMIO(VLV_DISPLAY_BASE + 0x70078)
5915 #define DSPFW7 _MMIO(VLV_DISPLAY_BASE + 0x7007c)
5916 #define DSPFW7_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
5925 #define DSPFW8_CHV _MMIO(VLV_DISPLAY_BASE + 0x700b8)
5934 #define DSPFW9_CHV _MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
5945 #define DSPHOWM _MMIO(VLV_DISPLAY_BASE + 0x70064)
5966 #define DSPHOWM1 _MMIO(VLV_DISPLAY_BASE + 0x70068)
5989 #define VLV_DDL(pipe) _MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
5997 #define CBR1_VLV _MMIO(VLV_DISPLAY_BASE + 0x70400)
6001 #define CBR4_VLV _MMIO(VLV_DISPLAY_BASE + 0x70450)
6498 #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
6521 #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
6522 #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
6523 #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
6524 #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
6525 #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
6526 #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
6527 #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
6528 #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
6529 #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
6530 #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
6532 #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
6535 #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
6538 #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
6540 #define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
6541 #define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
6542 #define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
6543 #define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
6544 #define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
6545 #define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
6546 #define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
6547 #define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
6548 #define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
6549 #define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
6550 #define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
6551 #define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
6552 #define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
6553 #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
6583 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
6930 #define VLV_VGACNTRL _MMIO(VLV_DISPLAY_BASE + 0x71400)
8169 #define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
8170 #define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
8171 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
8173 #define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
8174 #define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
8175 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
8177 #define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0)
8178 #define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4)
8179 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8)
8753 #define VLV_CHICKEN_3 _MMIO(VLV_DISPLAY_BASE + 0x7040C)
9019 #define _VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
9020 #define _VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
9022 #define _VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
9023 #define _VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
9025 #define VLV_AUD_CNTL_ST2 _MMIO(VLV_DISPLAY_BASE + 0x620C0)
9039 #define _VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
9040 #define _VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
10282 #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900)
10283 #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904)
10284 #define _CGM_PIPE_A_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x67908)
10285 #define _CGM_PIPE_A_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6790C)
10286 #define _CGM_PIPE_A_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x67910)
10287 #define _CGM_PIPE_A_DEGAMMA (VLV_DISPLAY_BASE + 0x66000)
10288 #define _CGM_PIPE_A_GAMMA (VLV_DISPLAY_BASE + 0x67000)
10289 #define _CGM_PIPE_A_MODE (VLV_DISPLAY_BASE + 0x67A00)
10294 #define _CGM_PIPE_B_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x69900)
10295 #define _CGM_PIPE_B_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x69904)
10296 #define _CGM_PIPE_B_CSC_COEFF45 (VLV_DISPLAY_BASE + 0x69908)
10297 #define _CGM_PIPE_B_CSC_COEFF67 (VLV_DISPLAY_BASE + 0x6990C)
10298 #define _CGM_PIPE_B_CSC_COEFF8 (VLV_DISPLAY_BASE + 0x69910)
10299 #define _CGM_PIPE_B_DEGAMMA (VLV_DISPLAY_BASE + 0x68000)
10300 #define _CGM_PIPE_B_GAMMA (VLV_DISPLAY_BASE + 0x69000)
10301 #define _CGM_PIPE_B_MODE (VLV_DISPLAY_BASE + 0x69A00)
10467 #define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
10468 #define _MIPIC_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
10563 #define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
10564 #define _MIPIC_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
10570 #define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)