Lines Matching defs:pw_idx
1150 #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) argument
1151 #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) argument
1152 #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) argument
1153 #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) argument
1154 #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) argument
9126 #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) argument
9127 #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) argument
9219 #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ argument
9225 #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ argument
9229 #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B) argument
9234 #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \ argument
9242 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) argument
9246 #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \ argument