Lines Matching refs:seq_printf
65 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); in i915_capabilities()
66 seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); in i915_capabilities()
67 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); in i915_capabilities()
143 seq_printf(m, "%pK: %c%c%c%c %8zdKiB %02x %02x %s%s%s", in describe_obj()
156 seq_printf(m, " (name: %d)", obj->base.name); in describe_obj()
168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", in describe_obj()
179 seq_printf(m, ", partial [%08llx+%x]", in describe_obj()
185 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", in describe_obj()
197 seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", in describe_obj()
214 seq_printf(m, " , fence: %d", vma->fence->id); in describe_obj()
221 seq_printf(m, " (pinned x %d)", pin_count); in describe_obj()
223 seq_printf(m, " (stolen: %08llx)", obj->stolen->start); in describe_obj()
225 seq_printf(m, " (global)"); in describe_obj()
229 seq_printf(m, " (%s)", engine->name); in describe_obj()
298 …seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu unbound, %llu closed)…
359 seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n", in i915_gem_object_info()
389 seq_printf(m, "Pipe %c power disabled\n", in gen8_display_interrupt_info()
393 seq_printf(m, "Pipe %c IMR:\t%08x\n", in gen8_display_interrupt_info()
396 seq_printf(m, "Pipe %c IIR:\t%08x\n", in gen8_display_interrupt_info()
399 seq_printf(m, "Pipe %c IER:\t%08x\n", in gen8_display_interrupt_info()
406 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", in gen8_display_interrupt_info()
408 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", in gen8_display_interrupt_info()
410 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", in gen8_display_interrupt_info()
413 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", in gen8_display_interrupt_info()
415 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", in gen8_display_interrupt_info()
417 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", in gen8_display_interrupt_info()
420 seq_printf(m, "PCU interrupt mask:\t%08x\n", in gen8_display_interrupt_info()
422 seq_printf(m, "PCU interrupt identity:\t%08x\n", in gen8_display_interrupt_info()
424 seq_printf(m, "PCU interrupt enable:\t%08x\n", in gen8_display_interrupt_info()
440 seq_printf(m, "Master Interrupt Control:\t%08x\n", in i915_interrupt_info()
443 seq_printf(m, "Display IER:\t%08x\n", in i915_interrupt_info()
445 seq_printf(m, "Display IIR:\t%08x\n", in i915_interrupt_info()
447 seq_printf(m, "Display IIR_RW:\t%08x\n", in i915_interrupt_info()
449 seq_printf(m, "Display IMR:\t%08x\n", in i915_interrupt_info()
458 seq_printf(m, "Pipe %c power disabled\n", in i915_interrupt_info()
463 seq_printf(m, "Pipe %c stat:\t%08x\n", in i915_interrupt_info()
471 seq_printf(m, "Port hotplug:\t%08x\n", in i915_interrupt_info()
473 seq_printf(m, "DPFLIPSTAT:\t%08x\n", in i915_interrupt_info()
475 seq_printf(m, "DPINVGTT:\t%08x\n", in i915_interrupt_info()
480 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", in i915_interrupt_info()
482 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", in i915_interrupt_info()
484 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", in i915_interrupt_info()
488 seq_printf(m, "PCU interrupt mask:\t%08x\n", in i915_interrupt_info()
490 seq_printf(m, "PCU interrupt identity:\t%08x\n", in i915_interrupt_info()
492 seq_printf(m, "PCU interrupt enable:\t%08x\n", in i915_interrupt_info()
495 seq_printf(m, "Master Interrupt Control: %08x\n", in i915_interrupt_info()
498 seq_printf(m, "Render/Copy Intr Enable: %08x\n", in i915_interrupt_info()
500 seq_printf(m, "VCS/VECS Intr Enable: %08x\n", in i915_interrupt_info()
502 seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", in i915_interrupt_info()
504 seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", in i915_interrupt_info()
506 seq_printf(m, "Crypto Intr Enable:\t %08x\n", in i915_interrupt_info()
508 seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", in i915_interrupt_info()
511 seq_printf(m, "Display Interrupt Control:\t%08x\n", in i915_interrupt_info()
516 seq_printf(m, "Master Interrupt Control:\t%08x\n", in i915_interrupt_info()
520 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n", in i915_interrupt_info()
522 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n", in i915_interrupt_info()
524 seq_printf(m, "GT Interrupt IER %d:\t%08x\n", in i915_interrupt_info()
530 seq_printf(m, "Display IER:\t%08x\n", in i915_interrupt_info()
532 seq_printf(m, "Display IIR:\t%08x\n", in i915_interrupt_info()
534 seq_printf(m, "Display IIR_RW:\t%08x\n", in i915_interrupt_info()
536 seq_printf(m, "Display IMR:\t%08x\n", in i915_interrupt_info()
546 seq_printf(m, "Pipe %c power disabled\n", in i915_interrupt_info()
551 seq_printf(m, "Pipe %c stat:\t%08x\n", in i915_interrupt_info()
557 seq_printf(m, "Master IER:\t%08x\n", in i915_interrupt_info()
560 seq_printf(m, "Render IER:\t%08x\n", in i915_interrupt_info()
562 seq_printf(m, "Render IIR:\t%08x\n", in i915_interrupt_info()
564 seq_printf(m, "Render IMR:\t%08x\n", in i915_interrupt_info()
567 seq_printf(m, "PM IER:\t\t%08x\n", in i915_interrupt_info()
569 seq_printf(m, "PM IIR:\t\t%08x\n", in i915_interrupt_info()
571 seq_printf(m, "PM IMR:\t\t%08x\n", in i915_interrupt_info()
574 seq_printf(m, "Port hotplug:\t%08x\n", in i915_interrupt_info()
576 seq_printf(m, "DPFLIPSTAT:\t%08x\n", in i915_interrupt_info()
578 seq_printf(m, "DPINVGTT:\t%08x\n", in i915_interrupt_info()
582 seq_printf(m, "Interrupt enable: %08x\n", in i915_interrupt_info()
584 seq_printf(m, "Interrupt identity: %08x\n", in i915_interrupt_info()
586 seq_printf(m, "Interrupt mask: %08x\n", in i915_interrupt_info()
589 seq_printf(m, "Pipe %c stat: %08x\n", in i915_interrupt_info()
593 seq_printf(m, "North Display Interrupt enable: %08x\n", in i915_interrupt_info()
595 seq_printf(m, "North Display Interrupt identity: %08x\n", in i915_interrupt_info()
597 seq_printf(m, "North Display Interrupt mask: %08x\n", in i915_interrupt_info()
599 seq_printf(m, "South Display Interrupt enable: %08x\n", in i915_interrupt_info()
601 seq_printf(m, "South Display Interrupt identity: %08x\n", in i915_interrupt_info()
603 seq_printf(m, "South Display Interrupt mask: %08x\n", in i915_interrupt_info()
605 seq_printf(m, "Graphics Interrupt enable: %08x\n", in i915_interrupt_info()
607 seq_printf(m, "Graphics Interrupt identity: %08x\n", in i915_interrupt_info()
609 seq_printf(m, "Graphics Interrupt mask: %08x\n", in i915_interrupt_info()
614 seq_printf(m, "RCS Intr Mask:\t %08x\n", in i915_interrupt_info()
616 seq_printf(m, "BCS Intr Mask:\t %08x\n", in i915_interrupt_info()
618 seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", in i915_interrupt_info()
620 seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", in i915_interrupt_info()
622 seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", in i915_interrupt_info()
624 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", in i915_interrupt_info()
626 seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", in i915_interrupt_info()
628 seq_printf(m, "Crypto Intr Mask:\t %08x\n", in i915_interrupt_info()
630 seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", in i915_interrupt_info()
635 seq_printf(m, in i915_interrupt_info()
651 seq_printf(m, "Total fences = %d\n", i915->ggtt.num_fences); in i915_gem_fence_regs_info()
658 seq_printf(m, "Fence %d, pin count = %d, object = ", in i915_gem_fence_regs_info()
785 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf); in i915_frequency_info()
786 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f); in i915_frequency_info()
787 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >> in i915_frequency_info()
789 seq_printf(m, "Current P-state: %d\n", in i915_frequency_info()
795 seq_printf(m, "Video Turbo Mode: %s\n", in i915_frequency_info()
797 seq_printf(m, "HW control enabled: %s\n", in i915_frequency_info()
799 seq_printf(m, "SW control enabled: %s\n", in i915_frequency_info()
807 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); in i915_frequency_info()
808 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); in i915_frequency_info()
810 seq_printf(m, "actual GPU freq: %d MHz\n", in i915_frequency_info()
813 seq_printf(m, "current GPU freq: %d MHz\n", in i915_frequency_info()
816 seq_printf(m, "max GPU freq: %d MHz\n", in i915_frequency_info()
819 seq_printf(m, "min GPU freq: %d MHz\n", in i915_frequency_info()
822 seq_printf(m, "idle GPU freq: %d MHz\n", in i915_frequency_info()
825 seq_printf(m, in i915_frequency_info()
901 seq_printf(m, "Video Turbo Mode: %s\n", in i915_frequency_info()
903 seq_printf(m, "HW control enabled: %s\n", in i915_frequency_info()
905 seq_printf(m, "SW control enabled: %s\n", in i915_frequency_info()
909 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", in i915_frequency_info()
912 seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", in i915_frequency_info()
914 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", in i915_frequency_info()
916 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); in i915_frequency_info()
917 seq_printf(m, "Render p-state ratio: %d\n", in i915_frequency_info()
919 seq_printf(m, "Render p-state VID: %d\n", in i915_frequency_info()
921 seq_printf(m, "Render p-state limit: %d\n", in i915_frequency_info()
923 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat); in i915_frequency_info()
924 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl); in i915_frequency_info()
925 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit); in i915_frequency_info()
926 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit); in i915_frequency_info()
927 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf); in i915_frequency_info()
928 seq_printf(m, "CAGF: %dMHz\n", cagf); in i915_frequency_info()
929 seq_printf(m, "RP CUR UP EI: %d (%dus)\n", in i915_frequency_info()
931 seq_printf(m, "RP CUR UP: %d (%dus)\n", in i915_frequency_info()
933 seq_printf(m, "RP PREV UP: %d (%dus)\n", in i915_frequency_info()
935 seq_printf(m, "Up threshold: %d%%\n", in i915_frequency_info()
938 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n", in i915_frequency_info()
940 seq_printf(m, "RP CUR DOWN: %d (%dus)\n", in i915_frequency_info()
942 seq_printf(m, "RP PREV DOWN: %d (%dus)\n", in i915_frequency_info()
944 seq_printf(m, "Down threshold: %d%%\n", in i915_frequency_info()
951 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", in i915_frequency_info()
957 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", in i915_frequency_info()
964 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", in i915_frequency_info()
966 seq_printf(m, "Max overclocked frequency: %dMHz\n", in i915_frequency_info()
969 seq_printf(m, "Current freq: %d MHz\n", in i915_frequency_info()
971 seq_printf(m, "Actual freq: %d MHz\n", cagf); in i915_frequency_info()
972 seq_printf(m, "Idle freq: %d MHz\n", in i915_frequency_info()
974 seq_printf(m, "Min freq: %d MHz\n", in i915_frequency_info()
976 seq_printf(m, "Boost freq: %d MHz\n", in i915_frequency_info()
978 seq_printf(m, "Max freq: %d MHz\n", in i915_frequency_info()
980 seq_printf(m, in i915_frequency_info()
987 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk); in i915_frequency_info()
988 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq); in i915_frequency_info()
989 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq); in i915_frequency_info()
1002 seq_printf(m, "\t\tINSTDONE: 0x%08x\n", in i915_instdone_info()
1008 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", in i915_instdone_info()
1015 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n", in i915_instdone_info()
1019 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n", in i915_instdone_info()
1031 seq_printf(m, "Reset flags: %lx\n", gt->reset.flags); in i915_hangcheck_info()
1043 seq_printf(m, "Hangcheck active, timer fires in %dms\n", in i915_hangcheck_info()
1051 seq_printf(m, "GT active? %s\n", yesno(gt->awake)); in i915_hangcheck_info()
1057 seq_printf(m, "%s: %d ms ago\n", in i915_hangcheck_info()
1062 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n", in i915_hangcheck_info()
1091 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN)); in ironlake_drpc_info()
1092 seq_printf(m, "Boost freq: %d\n", in ironlake_drpc_info()
1095 seq_printf(m, "HW control enabled: %s\n", in ironlake_drpc_info()
1097 seq_printf(m, "SW control enabled: %s\n", in ironlake_drpc_info()
1099 seq_printf(m, "Gated voltage change: %s\n", in ironlake_drpc_info()
1101 seq_printf(m, "Starting frequency: P%d\n", in ironlake_drpc_info()
1103 seq_printf(m, "Max P-state: P%d\n", in ironlake_drpc_info()
1105 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK)); in ironlake_drpc_info()
1106 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f)); in ironlake_drpc_info()
1107 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f)); in ironlake_drpc_info()
1108 seq_printf(m, "Render standby enabled: %s\n", in ironlake_drpc_info()
1145 seq_printf(m, "user.bypass_count = %u\n", in i915_forcewake_domains()
1149 seq_printf(m, "%s.wake_count = %u\n", in i915_forcewake_domains()
1162 seq_printf(m, "%s %u (%llu us)\n", in print_rc6_res()
1175 seq_printf(m, "RC6 Enabled: %s\n", in vlv_drpc_info()
1178 seq_printf(m, "Render Power Well: %s\n", in vlv_drpc_info()
1180 seq_printf(m, "Media Power Well: %s\n", in vlv_drpc_info()
1208 seq_printf(m, "RC1e Enabled: %s\n", in gen6_drpc_info()
1210 seq_printf(m, "RC6 Enabled: %s\n", in gen6_drpc_info()
1213 seq_printf(m, "Render Well Gating Enabled: %s\n", in gen6_drpc_info()
1215 seq_printf(m, "Media Well Gating Enabled: %s\n", in gen6_drpc_info()
1218 seq_printf(m, "Deep RC6 Enabled: %s\n", in gen6_drpc_info()
1220 seq_printf(m, "Deepest RC6 Enabled: %s\n", in gen6_drpc_info()
1244 seq_printf(m, "Core Power Down: %s\n", in gen6_drpc_info()
1247 seq_printf(m, "Render Power Well: %s\n", in gen6_drpc_info()
1250 seq_printf(m, "Media Power Well: %s\n", in gen6_drpc_info()
1263 seq_printf(m, "RC6 voltage: %dmV\n", in gen6_drpc_info()
1265 seq_printf(m, "RC6+ voltage: %dmV\n", in gen6_drpc_info()
1267 seq_printf(m, "RC6++ voltage: %dmV\n", in gen6_drpc_info()
1296 seq_printf(m, "FB tracking busy bits: 0x%08x\n", in i915_frontbuffer_tracking()
1299 seq_printf(m, "FB tracking flip bits: 0x%08x\n", in i915_frontbuffer_tracking()
1320 seq_printf(m, "FBC disabled: %s\n", fbc->no_fbc_reason); in i915_fbc_status()
1337 seq_printf(m, "Compressing: %s\n", yesno(mask)); in i915_fbc_status()
1393 seq_printf(m, "Enabled by kernel parameter: %s\n", in i915_ips_status()
1434 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled)); in i915_sr_status()
1466 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", in i915_ring_freq_table()
1525 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", in i915_gem_framebuffer_info()
1543 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ", in i915_gem_framebuffer_info()
1561 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)", in describe_ctx_ring()
1582 seq_printf(m, "%x [pin %u]", ctx->hw_id, in i915_context_status()
1589 seq_printf(m, "(%s [%d]) ", in i915_context_status()
1606 seq_printf(m, "%s: ", ce->engine->name); in i915_context_status()
1656 seq_printf(m, "bit6 swizzle for X-tiling = %s\n", in i915_swizzle_info()
1658 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", in i915_swizzle_info()
1662 seq_printf(m, "DDC = 0x%08x\n", in i915_swizzle_info()
1664 seq_printf(m, "DDC2 = 0x%08x\n", in i915_swizzle_info()
1666 seq_printf(m, "C0DRB3 = 0x%04x\n", in i915_swizzle_info()
1668 seq_printf(m, "C1DRB3 = 0x%04x\n", in i915_swizzle_info()
1671 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", in i915_swizzle_info()
1673 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", in i915_swizzle_info()
1675 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n", in i915_swizzle_info()
1677 seq_printf(m, "TILECTL = 0x%08x\n", in i915_swizzle_info()
1680 seq_printf(m, "GAMTARBMODE = 0x%08x\n", in i915_swizzle_info()
1683 seq_printf(m, "ARB_MODE = 0x%08x\n", in i915_swizzle_info()
1685 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", in i915_swizzle_info()
1731 seq_printf(m, "RPS enabled? %d\n", rps->enabled); in i915_rps_boost_info()
1732 seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake)); in i915_rps_boost_info()
1733 seq_printf(m, "Boosts outstanding? %d\n", in i915_rps_boost_info()
1735 seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive)); in i915_rps_boost_info()
1736 seq_printf(m, "Frequency requested %d, actual %d\n", in i915_rps_boost_info()
1739 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n", in i915_rps_boost_info()
1744 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n", in i915_rps_boost_info()
1749 seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts)); in i915_rps_boost_info()
1762 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n", in i915_rps_boost_info()
1764 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n", in i915_rps_boost_info()
1767 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n", in i915_rps_boost_info()
1782 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); in i915_llc()
1783 seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC", in i915_llc()
1802 seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); in i915_huc_load_status_info()
1823 seq_printf(m, "\nGuC status 0x%08x:\n", tmp); in i915_guc_load_status_info()
1824 seq_printf(m, "\tBootrom status = 0x%x\n", in i915_guc_load_status_info()
1826 seq_printf(m, "\tuKernel status = 0x%x\n", in i915_guc_load_status_info()
1828 seq_printf(m, "\tMIA Core status = 0x%x\n", in i915_guc_load_status_info()
1832 seq_printf(m, "\t%2d: \t0x%x\n", in i915_guc_load_status_info()
1870 seq_printf(m, "\tRelay full count: %u\n", in i915_guc_log_info()
1874 seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n", in i915_guc_log_info()
1897 seq_printf(m, "\nDoorbell map:\n"); in i915_guc_info()
1898 seq_printf(m, "\t%*pb\n", GUC_NUM_DOORBELLS, guc->doorbell_bitmap); in i915_guc_info()
1899 seq_printf(m, "Doorbell next cacheline: 0x%x\n", guc->db_cacheline); in i915_guc_info()
1901 seq_printf(m, "\nGuC execbuf client @ %p:\n", client); in i915_guc_info()
1902 seq_printf(m, "\tPriority %d, GuC stage index: %u, PD offset 0x%x\n", in i915_guc_info()
1906 seq_printf(m, "\tDoorbell id %d, offset: 0x%lx\n", in i915_guc_info()
1929 seq_printf(m, "GuC stage descriptor %u:\n", index); in i915_guc_stage_pool()
1930 seq_printf(m, "\tIndex: %u\n", desc->stage_id); in i915_guc_stage_pool()
1931 seq_printf(m, "\tAttribute: 0x%x\n", desc->attribute); in i915_guc_stage_pool()
1932 seq_printf(m, "\tPriority: %d\n", desc->priority); in i915_guc_stage_pool()
1933 seq_printf(m, "\tDoorbell id: %d\n", desc->db_id); in i915_guc_stage_pool()
1934 seq_printf(m, "\tEngines used: 0x%x\n", in i915_guc_stage_pool()
1936 seq_printf(m, "\tDoorbell trigger phy: 0x%llx, cpu: 0x%llx, uK: 0x%x\n", in i915_guc_stage_pool()
1940 seq_printf(m, "\tProcess descriptor: 0x%x\n", in i915_guc_stage_pool()
1942 seq_printf(m, "\tWorkqueue address: 0x%x, size: 0x%x\n", in i915_guc_stage_pool()
1951 seq_printf(m, "\t%s LRC:\n", engine->name); in i915_guc_stage_pool()
1952 seq_printf(m, "\t\tContext desc: 0x%x\n", in i915_guc_stage_pool()
1954 seq_printf(m, "\t\tContext id: 0x%x\n", lrc->context_id); in i915_guc_stage_pool()
1955 seq_printf(m, "\t\tLRCA: 0x%x\n", lrc->ring_lrca); in i915_guc_stage_pool()
1956 seq_printf(m, "\t\tRing begin: 0x%x\n", lrc->ring_begin); in i915_guc_stage_pool()
1957 seq_printf(m, "\t\tRing end: 0x%x\n", lrc->ring_end); in i915_guc_stage_pool()
1993 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n", in i915_guc_log_dump()
2107 seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str); in i915_psr_sink_status_show()
2159 seq_printf(m, "Source PSR status: %s [0x%08x]\n", status, val); in psr_source_status()
2174 seq_printf(m, "Sink support: %s", yesno(psr->sink_support)); in i915_edp_psr_status()
2176 seq_printf(m, " [0x%02x]", psr->dp->psr_dpcd[0]); in i915_edp_psr_status()
2189 seq_printf(m, "PSR mode: %s\n", status); in i915_edp_psr_status()
2201 seq_printf(m, "Source PSR ctl: %s [0x%08x]\n", in i915_edp_psr_status()
2204 seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", in i915_edp_psr_status()
2212 seq_printf(m, "Performance counter: %u\n", val); in i915_edp_psr_status()
2216 seq_printf(m, "Last attempted entry at: %lld\n", in i915_edp_psr_status()
2218 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); in i915_edp_psr_status()
2240 seq_printf(m, "%d\t%d\n", frame, su_blocks); in i915_edp_psr_status()
2306 seq_printf(m, "%llu", power); in i915_energy_uJ()
2319 seq_printf(m, "Runtime power status: %s\n", in i915_runtime_pm_status()
2322 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake)); in i915_runtime_pm_status()
2323 seq_printf(m, "IRQs disabled: %s\n", in i915_runtime_pm_status()
2326 seq_printf(m, "Usage count: %d\n", in i915_runtime_pm_status()
2329 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n"); in i915_runtime_pm_status()
2331 seq_printf(m, "PCI device power state: %s [%d]\n", in i915_runtime_pm_status()
2352 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count"); in i915_power_domain_info()
2358 seq_printf(m, "%-25s %d\n", power_well->desc->name, in i915_power_domain_info()
2362 seq_printf(m, " %-23s %d\n", in i915_power_domain_info()
2387 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL)); in i915_dmc_info()
2388 seq_printf(m, "path: %s\n", csr->fw_path); in i915_dmc_info()
2393 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), in i915_dmc_info()
2406 seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(dc5_reg)); in i915_dmc_info()
2408 seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(dc6_reg)); in i915_dmc_info()
2411 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0))); in i915_dmc_info()
2412 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE)); in i915_dmc_info()
2413 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL)); in i915_dmc_info()
2428 seq_printf(m, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); in intel_seq_print_mode()
2442 seq_printf(m, "\tencoder %d: type: %s, connectors:\n", in intel_encoder_info()
2446 seq_printf(m, "\t\tconnector %d: type: %s, status: %s", in intel_encoder_info()
2452 seq_printf(m, ", mode:\n"); in intel_encoder_info()
2470 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n", in intel_crtc_info()
2483 seq_printf(m, "\tfixed mode:\n"); in intel_panel_info()
2512 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]); in intel_dp_info()
2513 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio)); in intel_dp_info()
2536 seq_printf(m, "\taudio support: %s\n", yesno(has_audio)); in intel_dp_mst_info()
2545 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio)); in intel_hdmi_info()
2565 seq_printf(m, "connector %d: type %s, status: %s\n", in intel_connector_info()
2572 seq_printf(m, "\tphysical dimensions: %dx%dmm\n", in intel_connector_info()
2575 seq_printf(m, "\tsubpixel order: %s\n", in intel_connector_info()
2577 seq_printf(m, "\tCEA rev: %d\n", connector->display_info.cea_rev); in intel_connector_info()
2603 seq_printf(m, "\tmodes:\n"); in intel_connector_info()
2671 …seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%… in intel_plane_info()
2699 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d", in intel_scaler_info()
2708 seq_printf(m, ", scalers[%d]: use=%s, mode=%x", in intel_scaler_info()
2728 seq_printf(m, "CRTC info\n"); in i915_display_info()
2729 seq_printf(m, "---------\n"); in i915_display_info()
2736 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n", in i915_display_info()
2748 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x\n", in i915_display_info()
2759 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n", in i915_display_info()
2765 seq_printf(m, "\n"); in i915_display_info()
2766 seq_printf(m, "Connector info\n"); in i915_display_info()
2767 seq_printf(m, "--------------\n"); in i915_display_info()
2789 seq_printf(m, "GT awake? %s [%d]\n", in i915_engine_info()
2792 seq_printf(m, "CS timestamp frequency: %u kHz\n", in i915_engine_info()
2818 seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks); in i915_shrinker_info()
2819 seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch); in i915_shrinker_info()
2834 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->info->name, in i915_shared_dplls_info()
2836 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n", in i915_shared_dplls_info()
2838 seq_printf(m, " tracked hardware state:\n"); in i915_shared_dplls_info()
2839 seq_printf(m, " dpll: 0x%08x\n", pll->state.hw_state.dpll); in i915_shared_dplls_info()
2840 seq_printf(m, " dpll_md: 0x%08x\n", in i915_shared_dplls_info()
2842 seq_printf(m, " fp0: 0x%08x\n", pll->state.hw_state.fp0); in i915_shared_dplls_info()
2843 seq_printf(m, " fp1: 0x%08x\n", pll->state.hw_state.fp1); in i915_shared_dplls_info()
2844 seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll); in i915_shared_dplls_info()
2845 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
2846 seq_printf(m, " cfgcr1: 0x%08x\n", pll->state.hw_state.cfgcr1); in i915_shared_dplls_info()
2847 seq_printf(m, " mg_refclkin_ctl: 0x%08x\n", in i915_shared_dplls_info()
2849 seq_printf(m, " mg_clktop2_coreclkctl1: 0x%08x\n", in i915_shared_dplls_info()
2851 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", in i915_shared_dplls_info()
2853 seq_printf(m, " mg_pll_div0: 0x%08x\n", in i915_shared_dplls_info()
2855 seq_printf(m, " mg_pll_div1: 0x%08x\n", in i915_shared_dplls_info()
2857 seq_printf(m, " mg_pll_lf: 0x%08x\n", in i915_shared_dplls_info()
2859 seq_printf(m, " mg_pll_frac_lock: 0x%08x\n", in i915_shared_dplls_info()
2861 seq_printf(m, " mg_pll_ssc: 0x%08x\n", in i915_shared_dplls_info()
2863 seq_printf(m, " mg_pll_bias: 0x%08x\n", in i915_shared_dplls_info()
2865 seq_printf(m, " mg_pll_tdc_coldst_bias: 0x%08x\n", in i915_shared_dplls_info()
2887 seq_printf(m, "%s: Workarounds applied: %u\n", in i915_wa_registers()
2891 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n", in i915_wa_registers()
2895 seq_printf(m, "\n"); in i915_wa_registers()
2905 seq_printf(m, "Isochronous Priority Control: %s\n", in i915_ipc_status_show()
2965 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size"); in i915_ddb_info()
2973 seq_printf(m, "Pipe %c\n", pipe_name(pipe)); in i915_ddb_info()
2977 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane_id + 1, in i915_ddb_info()
2983 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start, in i915_ddb_info()
3007 seq_printf(m, "%s:\n", connector->name); in drrs_status_per_crtc()
3040 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X", in drrs_status_per_crtc()
3051 seq_printf(m, "DRRS_State: Unknown(%d)\n", in drrs_status_per_crtc()
3056 seq_printf(m, "\t\tVrefresh: %d", vrefresh); in drrs_status_per_crtc()
3078 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt); in i915_drrs_status()
3113 seq_printf(m, "MST Source Port %c\n", in i915_dp_mst_info()
3255 seq_printf(m, "%lx", in i915_displayport_test_data_show()
3259 seq_printf(m, "hdisplay: %d\n", in i915_displayport_test_data_show()
3261 seq_printf(m, "vdisplay: %d\n", in i915_displayport_test_data_show()
3263 seq_printf(m, "bpc: %u\n", in i915_displayport_test_data_show()
3297 seq_printf(m, "%02lx", intel_dp->compliance.test_type); in i915_displayport_test_type_show()
3340 seq_printf(m, "WM%d %u (%u.%u usec)\n", in wm_latency_show()
3908 seq_printf(m, " %s Slice Mask: %04x\n", type, in i915_print_sseu_info()
3910 seq_printf(m, " %s Slice Total: %u\n", type, in i915_print_sseu_info()
3912 seq_printf(m, " %s Subslice Total: %u\n", type, in i915_print_sseu_info()
3915 seq_printf(m, " %s Slice%i subslices: %u\n", type, in i915_print_sseu_info()
3918 seq_printf(m, " %s EU Total: %u\n", type, in i915_print_sseu_info()
3920 seq_printf(m, " %s EU Per Subslice: %u\n", type, in i915_print_sseu_info()
3926 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv))); in i915_print_sseu_info()
3928 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool); in i915_print_sseu_info()
3930 seq_printf(m, " Has Slice Power Gating: %s\n", in i915_print_sseu_info()
3932 seq_printf(m, " Has Subslice Power Gating: %s\n", in i915_print_sseu_info()
3934 seq_printf(m, " Has EU Power Gating: %s\n", in i915_print_sseu_info()
4019 seq_printf(m, "Threshold: %d\n", hotplug->hpd_storm_threshold); in i915_hpd_storm_ctl_show()
4020 seq_printf(m, "Detected: %s\n", in i915_hpd_storm_ctl_show()
4093 seq_printf(m, "Enabled: %s\n", in i915_hpd_short_storm_ctl_show()
4437 seq_printf(m, "%04x: ERROR %d\n", b->offset, (int)err); in i915_dpcd_show()
4439 seq_printf(m, "%04x: %*ph\n", b->offset, (int)err, buf); in i915_dpcd_show()
4455 seq_printf(m, "Panel power up delay: %d\n", in i915_panel_show()
4457 seq_printf(m, "Panel power down delay: %d\n", in i915_panel_show()
4459 seq_printf(m, "Backlight on delay: %d\n", in i915_panel_show()
4461 seq_printf(m, "Backlight off delay: %d\n", in i915_panel_show()
4480 seq_printf(m, "%s:%d HDCP version: ", connector->name, in i915_hdcp_sink_capability_show()
4530 seq_printf(m, "DSC_Enabled: %s\n", in i915_dsc_fec_support_show()
4532 seq_printf(m, "DSC_Sink_Support: %s\n", in i915_dsc_fec_support_show()
4534 seq_printf(m, "Force_DSC_Enable: %s\n", in i915_dsc_fec_support_show()
4537 seq_printf(m, "FEC_Sink_Support: %s\n", in i915_dsc_fec_support_show()