78 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,  in write_vreg()  function
236 	write_vreg(vgpu, offset, p_data, bytes);  in gamw_echo_dev_rw_ia_write()
263 	write_vreg(vgpu, off, p_data, bytes);  in fence_mmio_write()
317 	write_vreg(vgpu, offset, p_data, bytes);  in gdrst_mmio_write()
371 	write_vreg(vgpu, offset, p_data, bytes);  in pch_pp_control_mmio_write()
389 	write_vreg(vgpu, offset, p_data, bytes);  in transconf_mmio_write()
401 	write_vreg(vgpu, offset, p_data, bytes);  in lcpll_ctl_mmio_write()
445 	write_vreg(vgpu, offset, p_data, bytes);  in pipeconf_mmio_write()
539 	write_vreg(vgpu, offset, p_data, bytes);  in ddi_buf_ctl_mmio_write()
661 	write_vreg(vgpu, offset, p_data, bytes);  in update_fdi_rx_iir_status()
694 	write_vreg(vgpu, offset, p_data, bytes);  in dp_tp_ctl_mmio_write()
725 	write_vreg(vgpu, offset, p_data, bytes);  in pch_adpa_mmio_write()
738 	write_vreg(vgpu, offset, p_data, bytes);  in south_chicken2_mmio_write()
758 	write_vreg(vgpu, offset, p_data, bytes);  in pri_surf_mmio_write()
780 	write_vreg(vgpu, offset, p_data, bytes);  in spr_surf_mmio_write()
800 	write_vreg(vgpu, offset, p_data, bytes);  in reg50080_mmio_write()
916 	write_vreg(vgpu, offset, p_data, bytes);  in dp_aux_ch_ctl_mmio_write()
1075 	write_vreg(vgpu, offset, p_data, bytes);  in mbctl_write()
1084 	write_vreg(vgpu, offset, p_data, bytes);  in vga_control_mmio_write()
1152 	write_vreg(vgpu, offset, p_data, bytes);  in sbi_ctl_mmio_write()
1293 		write_vreg(vgpu, offset, p_data, bytes);  in pvinfo_mmio_write()
1317 	write_vreg(vgpu, offset, p_data, bytes);  in power_well_ctl_mmio_write()
1332 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_dbuf_ctl_mmio_write()
1345 	write_vreg(vgpu, offset, p_data, bytes);  in fpga_dbg_mmio_write()
1357 	write_vreg(vgpu, offset, p_data, bytes);  in dma_ctrl_write()
1379 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_trtte_write()
1387 	write_vreg(vgpu, offset, p_data, bytes);  in gen9_trtt_chicken_write()
1701 	write_vreg(vgpu, offset, p_data, bytes);  in ring_mode_mmio_write()
1751 	write_vreg(vgpu, offset, p_data, bytes);  in gvt_reg_tlb_control_handler()
1783 	write_vreg(vgpu, offset, p_data, bytes);  in ring_reset_ctl_write()
1802 	write_vreg(vgpu, offset, p_data, bytes);  in csfe_chicken1_mmio_write()
3461 	write_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_default_mmio_write()
3481 	write_vreg(vgpu, offset, p_data, bytes);  in intel_vgpu_mask_mmio_write()