Lines Matching refs:R_VCS

413 #define R_VCS	(R_VCS1 | R_VCS2)  macro
416 #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
2524 		R_VCS, D_ALL, 0, 12, NULL},
2527 		R_VCS, D_ALL, 0, 12, NULL},
2530 		R_VCS, D_BDW_PLUS, 0, 12, NULL},
2533 		F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2536 		F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2538 	{"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2541 		R_VCS, D_ALL, 0, 12, NULL},
2544 		R_VCS, D_ALL, 0, 12, NULL},
2547 		R_VCS, D_ALL, 0, 12, NULL},
2550 		R_VCS, D_ALL, 0, 12, NULL},
2553 		R_VCS, D_ALL, 0, 12, NULL},
2556 		R_VCS, D_ALL, 0, 12, NULL},
2559 		R_VCS, D_ALL, 0, 6, NULL},
2562 		R_VCS, D_ALL, 0, 12, NULL},
2565 		R_VCS, D_ALL, 0, 12, NULL},
2568 		R_VCS, D_ALL, 0, 12, NULL},
2571 		R_VCS, D_ALL, 0, 12, NULL},
2574 		R_VCS, D_ALL, 0, 12, NULL},
2577 		R_VCS, D_ALL, 0, 12, NULL},
2580 		R_VCS, D_ALL, 0, 12, NULL},
2582 		R_VCS, D_ALL, 0, 12, NULL},
2585 		R_VCS, D_ALL, 0, 12, NULL},
2588 		R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2591 		R_VCS, D_ALL, 0, 12, NULL},
2594 		R_VCS, D_ALL, 0, 12, NULL},
2597 		R_VCS, D_ALL, 0, 12, NULL},
2600 		R_VCS, D_ALL, 0, 12, NULL},
2603 		R_VCS, D_ALL, 0, 12, NULL},
2606 		R_VCS, D_ALL, 0, 12, NULL},
2609 		R_VCS, D_ALL, 0, 12, NULL},
2612 		R_VCS, D_ALL, 0, 12, NULL},
2615 		R_VCS, D_ALL, 0, 12, NULL},
2618 		R_VCS, D_ALL, 0, 12, NULL},
2621 		R_VCS, D_ALL, 0, 12, NULL},
2623 	{"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2626 	{"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2628 	{"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2631 		R_VCS, D_ALL, 0, 12, NULL},
2634 		R_VCS, D_ALL, 0, 12, NULL},
2637 		R_VCS, D_ALL, 0, 12, NULL},