Lines Matching refs:engine
80 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen2_render_ring_flush()
154 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen4_render_ring_flush()
164 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen4_render_ring_flush()
219 intel_gt_scratch_offset(rq->engine->gt, in gen6_emit_post_sync_nonzero_flush()
254 intel_gt_scratch_offset(rq->engine->gt, in gen6_render_ring_flush()
313 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in gen6_rcs_emit_breadcrumb()
359 intel_gt_scratch_offset(rq->engine->gt, in gen7_render_ring_flush()
442 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); in gen6_xcs_emit_breadcrumb()
462 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); in gen7_xcs_emit_breadcrumb()
489 static void set_hwstam(struct intel_engine_cs *engine, u32 mask) in set_hwstam() argument
495 if (engine->class == RENDER_CLASS) { in set_hwstam()
496 if (INTEL_GEN(engine->i915) >= 6) in set_hwstam()
502 intel_engine_set_hwsp_writemask(engine, mask); in set_hwstam()
505 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys) in set_hws_pga() argument
507 struct drm_i915_private *dev_priv = engine->i915; in set_hws_pga()
517 static struct page *status_page(struct intel_engine_cs *engine) in status_page() argument
519 struct drm_i915_gem_object *obj = engine->status_page.vma->obj; in status_page()
525 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) in ring_setup_phys_status_page() argument
527 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine)))); in ring_setup_phys_status_page()
528 set_hwstam(engine, ~0u); in ring_setup_phys_status_page()
531 static void set_hwsp(struct intel_engine_cs *engine, u32 offset) in set_hwsp() argument
533 struct drm_i915_private *dev_priv = engine->i915; in set_hwsp()
541 switch (engine->id) { in set_hwsp()
547 GEM_BUG_ON(engine->id); in set_hwsp()
563 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base); in set_hwsp()
565 hwsp = RING_HWS_PGA(engine->mmio_base); in set_hwsp()
572 static void flush_cs_tlb(struct intel_engine_cs *engine) in flush_cs_tlb() argument
574 struct drm_i915_private *dev_priv = engine->i915; in flush_cs_tlb()
580 WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in flush_cs_tlb()
582 ENGINE_WRITE(engine, RING_INSTPM, in flush_cs_tlb()
585 if (intel_wait_for_register(engine->uncore, in flush_cs_tlb()
586 RING_INSTPM(engine->mmio_base), in flush_cs_tlb()
590 engine->name); in flush_cs_tlb()
593 static void ring_setup_status_page(struct intel_engine_cs *engine) in ring_setup_status_page() argument
595 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma)); in ring_setup_status_page()
596 set_hwstam(engine, ~0u); in ring_setup_status_page()
598 flush_cs_tlb(engine); in ring_setup_status_page()
601 static bool stop_ring(struct intel_engine_cs *engine) in stop_ring() argument
603 struct drm_i915_private *dev_priv = engine->i915; in stop_ring()
606 ENGINE_WRITE(engine, in stop_ring()
608 if (intel_wait_for_register(engine->uncore, in stop_ring()
609 RING_MI_MODE(engine->mmio_base), in stop_ring()
614 engine->name); in stop_ring()
621 if (ENGINE_READ(engine, RING_HEAD) != in stop_ring()
622 ENGINE_READ(engine, RING_TAIL)) in stop_ring()
627 ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL)); in stop_ring()
629 ENGINE_WRITE(engine, RING_HEAD, 0); in stop_ring()
630 ENGINE_WRITE(engine, RING_TAIL, 0); in stop_ring()
633 ENGINE_WRITE(engine, RING_CTL, 0); in stop_ring()
635 return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0; in stop_ring()
638 static int xcs_resume(struct intel_engine_cs *engine) in xcs_resume() argument
640 struct drm_i915_private *dev_priv = engine->i915; in xcs_resume()
641 struct intel_ring *ring = engine->legacy.ring; in xcs_resume()
645 engine->name, ring->head, ring->tail); in xcs_resume()
647 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL); in xcs_resume()
650 if (!stop_ring(engine)) { in xcs_resume()
654 engine->name, in xcs_resume()
655 ENGINE_READ(engine, RING_CTL), in xcs_resume()
656 ENGINE_READ(engine, RING_HEAD), in xcs_resume()
657 ENGINE_READ(engine, RING_TAIL), in xcs_resume()
658 ENGINE_READ(engine, RING_START)); in xcs_resume()
660 if (!stop_ring(engine)) { in xcs_resume()
663 engine->name, in xcs_resume()
664 ENGINE_READ(engine, RING_CTL), in xcs_resume()
665 ENGINE_READ(engine, RING_HEAD), in xcs_resume()
666 ENGINE_READ(engine, RING_TAIL), in xcs_resume()
667 ENGINE_READ(engine, RING_START)); in xcs_resume()
674 ring_setup_phys_status_page(engine); in xcs_resume()
676 ring_setup_status_page(engine); in xcs_resume()
678 intel_engine_reset_breadcrumbs(engine); in xcs_resume()
681 ENGINE_POSTING_READ(engine, RING_HEAD); in xcs_resume()
689 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma)); in xcs_resume()
697 ENGINE_WRITE(engine, RING_HEAD, ring->head); in xcs_resume()
698 ENGINE_WRITE(engine, RING_TAIL, ring->head); in xcs_resume()
699 ENGINE_POSTING_READ(engine, RING_TAIL); in xcs_resume()
701 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID); in xcs_resume()
704 if (intel_wait_for_register(engine->uncore, in xcs_resume()
705 RING_CTL(engine->mmio_base), in xcs_resume()
710 engine->name, in xcs_resume()
711 ENGINE_READ(engine, RING_CTL), in xcs_resume()
712 ENGINE_READ(engine, RING_CTL) & RING_VALID, in xcs_resume()
713 ENGINE_READ(engine, RING_HEAD), ring->head, in xcs_resume()
714 ENGINE_READ(engine, RING_TAIL), ring->tail, in xcs_resume()
715 ENGINE_READ(engine, RING_START), in xcs_resume()
722 ENGINE_WRITE(engine, in xcs_resume()
727 ENGINE_WRITE(engine, RING_TAIL, ring->tail); in xcs_resume()
728 ENGINE_POSTING_READ(engine, RING_TAIL); in xcs_resume()
732 intel_engine_queue_breadcrumbs(engine); in xcs_resume()
734 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL); in xcs_resume()
739 static void reset_prepare(struct intel_engine_cs *engine) in reset_prepare() argument
741 struct intel_uncore *uncore = engine->uncore; in reset_prepare()
742 const u32 base = engine->mmio_base; in reset_prepare()
758 GEM_TRACE("%s\n", engine->name); in reset_prepare()
760 if (intel_engine_stop_cs(engine)) in reset_prepare()
761 GEM_TRACE("%s: timed out on STOP_RING\n", engine->name); in reset_prepare()
778 engine->name, in reset_prepare()
782 static void reset_ring(struct intel_engine_cs *engine, bool stalled) in reset_ring() argument
789 spin_lock_irqsave(&engine->active.lock, flags); in reset_ring()
790 list_for_each_entry(pos, &engine->active.requests, sched.link) { in reset_ring()
837 GEM_BUG_ON(rq->ring != engine->legacy.ring); in reset_ring()
840 head = engine->legacy.ring->tail; in reset_ring()
842 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head); in reset_ring()
844 spin_unlock_irqrestore(&engine->active.lock, flags); in reset_ring()
847 static void reset_finish(struct intel_engine_cs *engine) in reset_finish() argument
851 static int rcs_resume(struct intel_engine_cs *engine) in rcs_resume() argument
853 struct drm_i915_private *dev_priv = engine->i915; in rcs_resume()
907 return xcs_resume(engine); in rcs_resume()
910 static void cancel_requests(struct intel_engine_cs *engine) in cancel_requests() argument
915 spin_lock_irqsave(&engine->active.lock, flags); in cancel_requests()
918 list_for_each_entry(request, &engine->active.requests, sched.link) { in cancel_requests()
927 spin_unlock_irqrestore(&engine->active.lock, flags); in cancel_requests()
934 ENGINE_WRITE(request->engine, RING_TAIL, in i9xx_submit_request()
940 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); in i9xx_emit_breadcrumb()
963 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma); in gen5_emit_breadcrumb()
985 gen5_irq_enable(struct intel_engine_cs *engine) in gen5_irq_enable() argument
987 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); in gen5_irq_enable()
991 gen5_irq_disable(struct intel_engine_cs *engine) in gen5_irq_disable() argument
993 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); in gen5_irq_disable()
997 i9xx_irq_enable(struct intel_engine_cs *engine) in i9xx_irq_enable() argument
999 engine->i915->irq_mask &= ~engine->irq_enable_mask; in i9xx_irq_enable()
1000 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); in i9xx_irq_enable()
1001 intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR); in i9xx_irq_enable()
1005 i9xx_irq_disable(struct intel_engine_cs *engine) in i9xx_irq_disable() argument
1007 engine->i915->irq_mask |= engine->irq_enable_mask; in i9xx_irq_disable()
1008 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask); in i9xx_irq_disable()
1012 i8xx_irq_enable(struct intel_engine_cs *engine) in i8xx_irq_enable() argument
1014 struct drm_i915_private *i915 = engine->i915; in i8xx_irq_enable()
1016 i915->irq_mask &= ~engine->irq_enable_mask; in i8xx_irq_enable()
1018 ENGINE_POSTING_READ16(engine, RING_IMR); in i8xx_irq_enable()
1022 i8xx_irq_disable(struct intel_engine_cs *engine) in i8xx_irq_disable() argument
1024 struct drm_i915_private *i915 = engine->i915; in i8xx_irq_disable()
1026 i915->irq_mask |= engine->irq_enable_mask; in i8xx_irq_disable()
1046 gen6_irq_enable(struct intel_engine_cs *engine) in gen6_irq_enable() argument
1048 ENGINE_WRITE(engine, RING_IMR, in gen6_irq_enable()
1049 ~(engine->irq_enable_mask | engine->irq_keep_mask)); in gen6_irq_enable()
1052 ENGINE_POSTING_READ(engine, RING_IMR); in gen6_irq_enable()
1054 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); in gen6_irq_enable()
1058 gen6_irq_disable(struct intel_engine_cs *engine) in gen6_irq_disable() argument
1060 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask); in gen6_irq_disable()
1061 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); in gen6_irq_disable()
1065 hsw_vebox_irq_enable(struct intel_engine_cs *engine) in hsw_vebox_irq_enable() argument
1067 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); in hsw_vebox_irq_enable()
1070 ENGINE_POSTING_READ(engine, RING_IMR); in hsw_vebox_irq_enable()
1072 gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); in hsw_vebox_irq_enable()
1076 hsw_vebox_irq_disable(struct intel_engine_cs *engine) in hsw_vebox_irq_disable() argument
1078 ENGINE_WRITE(engine, RING_IMR, ~0); in hsw_vebox_irq_disable()
1079 gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); in hsw_vebox_irq_disable()
1111 intel_gt_scratch_offset(rq->engine->gt, in i830_emit_bb_start()
1114 GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE); in i830_emit_bb_start()
1299 intel_engine_create_ring(struct intel_engine_cs *engine, int size) in intel_engine_create_ring() argument
1301 struct drm_i915_private *i915 = engine->i915; in intel_engine_create_ring()
1325 vma = create_ring_vma(engine->gt->ggtt, size); in intel_engine_create_ring()
1401 alloc_context_vma(struct intel_engine_cs *engine) in alloc_context_vma() argument
1403 struct drm_i915_private *i915 = engine->i915; in alloc_context_vma()
1408 obj = i915_gem_object_create_shmem(i915, engine->context_size); in alloc_context_vma()
1430 if (engine->default_state) { in alloc_context_vma()
1439 defaults = i915_gem_object_pin_map(engine->default_state, in alloc_context_vma()
1446 memcpy(vaddr, defaults, engine->context_size); in alloc_context_vma()
1447 i915_gem_object_unpin_map(engine->default_state); in alloc_context_vma()
1453 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL); in alloc_context_vma()
1470 struct intel_engine_cs *engine = ce->engine; in ring_context_alloc() local
1473 GEM_BUG_ON(!engine->legacy.ring); in ring_context_alloc()
1474 ce->ring = engine->legacy.ring; in ring_context_alloc()
1475 ce->timeline = intel_timeline_get(engine->legacy.timeline); in ring_context_alloc()
1478 if (engine->context_size) { in ring_context_alloc()
1481 vma = alloc_context_vma(engine); in ring_context_alloc()
1530 const struct intel_engine_cs * const engine = rq->engine; in load_pd_dir() local
1538 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
1542 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
1552 const struct intel_engine_cs * const engine = rq->engine; in flush_pd_dir() local
1561 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in flush_pd_dir()
1562 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in flush_pd_dir()
1573 struct intel_engine_cs *engine = rq->engine; in mi_set_context() local
1613 if (signaller == engine) in mi_set_context()
1646 *cs++ = i915_ggtt_offset(engine->kernel_context->state) | in mi_set_context()
1667 if (signaller == engine) in mi_set_context()
1679 *cs++ = intel_gt_scratch_offset(rq->engine->gt, in mi_set_context()
1744 struct intel_engine_cs *engine = rq->engine; in switch_context() local
1766 if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915)) in switch_context()
1775 if (ppgtt->pd_dirty_engines & engine->mask) { in switch_context()
1776 unwind_mm = engine->mask; in switch_context()
1783 GEM_BUG_ON(engine->id != RCS0); in switch_context()
1801 ret = engine->emit_flush(rq, EMIT_INVALIDATE); in switch_context()
1817 ret = engine->emit_flush(rq, EMIT_INVALIDATE); in switch_context()
1821 ret = engine->emit_flush(rq, EMIT_FLUSH); in switch_context()
1854 ret = request->engine->emit_flush(request, EMIT_INVALIDATE); in ring_request_alloc()
2008 struct intel_uncore *uncore = request->engine->uncore; in gen6_bsd_submit_request()
2136 static void i9xx_set_default_submission(struct intel_engine_cs *engine) in i9xx_set_default_submission() argument
2138 engine->submit_request = i9xx_submit_request; in i9xx_set_default_submission()
2139 engine->cancel_requests = cancel_requests; in i9xx_set_default_submission()
2141 engine->park = NULL; in i9xx_set_default_submission()
2142 engine->unpark = NULL; in i9xx_set_default_submission()
2145 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) in gen6_bsd_set_default_submission() argument
2147 i9xx_set_default_submission(engine); in gen6_bsd_set_default_submission()
2148 engine->submit_request = gen6_bsd_submit_request; in gen6_bsd_set_default_submission()
2151 static void ring_destroy(struct intel_engine_cs *engine) in ring_destroy() argument
2153 struct drm_i915_private *dev_priv = engine->i915; in ring_destroy()
2156 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0); in ring_destroy()
2158 intel_engine_cleanup_common(engine); in ring_destroy()
2160 intel_ring_unpin(engine->legacy.ring); in ring_destroy()
2161 intel_ring_put(engine->legacy.ring); in ring_destroy()
2163 intel_timeline_unpin(engine->legacy.timeline); in ring_destroy()
2164 intel_timeline_put(engine->legacy.timeline); in ring_destroy()
2166 kfree(engine); in ring_destroy()
2169 static void setup_irq(struct intel_engine_cs *engine) in setup_irq() argument
2171 struct drm_i915_private *i915 = engine->i915; in setup_irq()
2174 engine->irq_enable = gen6_irq_enable; in setup_irq()
2175 engine->irq_disable = gen6_irq_disable; in setup_irq()
2177 engine->irq_enable = gen5_irq_enable; in setup_irq()
2178 engine->irq_disable = gen5_irq_disable; in setup_irq()
2180 engine->irq_enable = i9xx_irq_enable; in setup_irq()
2181 engine->irq_disable = i9xx_irq_disable; in setup_irq()
2183 engine->irq_enable = i8xx_irq_enable; in setup_irq()
2184 engine->irq_disable = i8xx_irq_disable; in setup_irq()
2188 static void setup_common(struct intel_engine_cs *engine) in setup_common() argument
2190 struct drm_i915_private *i915 = engine->i915; in setup_common()
2195 setup_irq(engine); in setup_common()
2197 engine->destroy = ring_destroy; in setup_common()
2199 engine->resume = xcs_resume; in setup_common()
2200 engine->reset.prepare = reset_prepare; in setup_common()
2201 engine->reset.reset = reset_ring; in setup_common()
2202 engine->reset.finish = reset_finish; in setup_common()
2204 engine->cops = &ring_context_ops; in setup_common()
2205 engine->request_alloc = ring_request_alloc; in setup_common()
2212 engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb; in setup_common()
2214 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb; in setup_common()
2216 engine->set_default_submission = i9xx_set_default_submission; in setup_common()
2219 engine->emit_bb_start = gen6_emit_bb_start; in setup_common()
2221 engine->emit_bb_start = i965_emit_bb_start; in setup_common()
2223 engine->emit_bb_start = i830_emit_bb_start; in setup_common()
2225 engine->emit_bb_start = i915_emit_bb_start; in setup_common()
2228 static void setup_rcs(struct intel_engine_cs *engine) in setup_rcs() argument
2230 struct drm_i915_private *i915 = engine->i915; in setup_rcs()
2233 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in setup_rcs()
2235 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in setup_rcs()
2238 engine->emit_flush = gen7_render_ring_flush; in setup_rcs()
2239 engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb; in setup_rcs()
2241 engine->emit_flush = gen6_render_ring_flush; in setup_rcs()
2242 engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb; in setup_rcs()
2244 engine->emit_flush = gen4_render_ring_flush; in setup_rcs()
2247 engine->emit_flush = gen2_render_ring_flush; in setup_rcs()
2249 engine->emit_flush = gen4_render_ring_flush; in setup_rcs()
2250 engine->irq_enable_mask = I915_USER_INTERRUPT; in setup_rcs()
2254 engine->emit_bb_start = hsw_emit_bb_start; in setup_rcs()
2256 engine->resume = rcs_resume; in setup_rcs()
2259 static void setup_vcs(struct intel_engine_cs *engine) in setup_vcs() argument
2261 struct drm_i915_private *i915 = engine->i915; in setup_vcs()
2266 engine->set_default_submission = gen6_bsd_set_default_submission; in setup_vcs()
2267 engine->emit_flush = gen6_bsd_ring_flush; in setup_vcs()
2268 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in setup_vcs()
2271 engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; in setup_vcs()
2273 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; in setup_vcs()
2275 engine->emit_flush = bsd_ring_flush; in setup_vcs()
2277 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in setup_vcs()
2279 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in setup_vcs()
2283 static void setup_bcs(struct intel_engine_cs *engine) in setup_bcs() argument
2285 struct drm_i915_private *i915 = engine->i915; in setup_bcs()
2287 engine->emit_flush = gen6_ring_flush; in setup_bcs()
2288 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in setup_bcs()
2291 engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb; in setup_bcs()
2293 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; in setup_bcs()
2296 static void setup_vecs(struct intel_engine_cs *engine) in setup_vecs() argument
2298 struct drm_i915_private *i915 = engine->i915; in setup_vecs()
2302 engine->emit_flush = gen6_ring_flush; in setup_vecs()
2303 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in setup_vecs()
2304 engine->irq_enable = hsw_vebox_irq_enable; in setup_vecs()
2305 engine->irq_disable = hsw_vebox_irq_disable; in setup_vecs()
2307 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb; in setup_vecs()
2310 int intel_ring_submission_setup(struct intel_engine_cs *engine) in intel_ring_submission_setup() argument
2312 setup_common(engine); in intel_ring_submission_setup()
2314 switch (engine->class) { in intel_ring_submission_setup()
2316 setup_rcs(engine); in intel_ring_submission_setup()
2319 setup_vcs(engine); in intel_ring_submission_setup()
2322 setup_bcs(engine); in intel_ring_submission_setup()
2325 setup_vecs(engine); in intel_ring_submission_setup()
2328 MISSING_CASE(engine->class); in intel_ring_submission_setup()
2335 int intel_ring_submission_init(struct intel_engine_cs *engine) in intel_ring_submission_init() argument
2341 timeline = intel_timeline_create(engine->gt, engine->status_page.vma); in intel_ring_submission_init()
2352 ring = intel_engine_create_ring(engine, SZ_16K); in intel_ring_submission_init()
2362 GEM_BUG_ON(engine->legacy.ring); in intel_ring_submission_init()
2363 engine->legacy.ring = ring; in intel_ring_submission_init()
2364 engine->legacy.timeline = timeline; in intel_ring_submission_init()
2366 err = intel_engine_init_common(engine); in intel_ring_submission_init()
2370 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); in intel_ring_submission_init()
2383 intel_engine_cleanup_common(engine); in intel_ring_submission_init()