Lines Matching +full:panel +full:- +full:lvds
2 * Copyright © 2006-2007 Intel Corporation
50 /* Private structure for the integrated LVDS support */
102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_hw_state()
103 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_lvds_get_hw_state()
108 encoder->power_domain); in intel_lvds_get_hw_state()
112 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_config()
123 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_lvds_get_config()
126 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
128 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_config()
138 pipe_config->base.adjusted_mode.flags |= flags; in intel_lvds_get_config()
141 pipe_config->gmch_pfit.lvds_border_bits = in intel_lvds_get_config()
148 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
151 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_lvds_get_config()
159 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
162 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
163 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
164 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
168 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
175 * too short power-cycle delay due to the asynchronous programming of in intel_lvds_pps_get_hw_state()
179 val--; in intel_lvds_pps_get_hw_state()
181 pps->t4 = val * 1000; in intel_lvds_pps_get_hw_state()
184 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { in intel_lvds_pps_get_hw_state()
185 DRM_DEBUG_KMS("Panel power timings uninitialized, " in intel_lvds_pps_get_hw_state()
188 pps->t1_t2 = 40 * 10; in intel_lvds_pps_get_hw_state()
189 pps->t5 = 200 * 10; in intel_lvds_pps_get_hw_state()
191 pps->t3 = 35 * 10; in intel_lvds_pps_get_hw_state()
192 pps->tx = 200 * 10; in intel_lvds_pps_get_hw_state()
195 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " in intel_lvds_pps_get_hw_state()
197 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, in intel_lvds_pps_get_hw_state()
198 pps->divider, pps->port, pps->powerdown_on_reset); in intel_lvds_pps_get_hw_state()
208 if (pps->powerdown_on_reset) in intel_lvds_pps_init_hw()
213 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | in intel_lvds_pps_init_hw()
214 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | in intel_lvds_pps_init_hw()
215 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); in intel_lvds_pps_init_hw()
218 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | in intel_lvds_pps_init_hw()
219 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); in intel_lvds_pps_init_hw()
222 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | in intel_lvds_pps_init_hw()
224 DIV_ROUND_UP(pps->t4, 1000) + 1)); in intel_lvds_pps_init_hw()
231 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_pre_enable_lvds()
232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_pre_enable_lvds()
233 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); in intel_pre_enable_lvds()
234 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_pre_enable_lvds()
235 int pipe = crtc->pipe; in intel_pre_enable_lvds()
241 pipe_config->shared_dpll); in intel_pre_enable_lvds()
246 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); in intel_pre_enable_lvds()
248 temp = lvds_encoder->init_lvds_val; in intel_pre_enable_lvds()
261 temp |= pipe_config->gmch_pfit.lvds_border_bits; in intel_pre_enable_lvds()
264 * Set the B0-B3 data pairs corresponding to whether we're going to in intel_pre_enable_lvds()
265 * set the DPLLs for dual-channel mode or not. in intel_pre_enable_lvds()
267 if (lvds_encoder->is_dual_link) in intel_pre_enable_lvds()
273 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) in intel_pre_enable_lvds()
279 temp |= lvds_encoder->a3_power; in intel_pre_enable_lvds()
282 * Set the dithering flag on LVDS as needed, note that there is no in intel_pre_enable_lvds()
283 * special lvds dither control bit on pch-split platforms, dithering is in intel_pre_enable_lvds()
288 * Bspec wording suggests that LVDS port dithering only exists in intel_pre_enable_lvds()
291 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
297 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) in intel_pre_enable_lvds()
299 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) in intel_pre_enable_lvds()
302 I915_WRITE(lvds_encoder->reg, temp); in intel_pre_enable_lvds()
306 * Sets the power state for the panel.
312 struct drm_device *dev = encoder->base.dev; in intel_enable_lvds()
313 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_enable_lvds()
316 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
319 POSTING_READ(lvds_encoder->reg); in intel_enable_lvds()
322 DRM_ERROR("timed out waiting for panel to power on\n"); in intel_enable_lvds()
331 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); in intel_disable_lvds()
332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_disable_lvds()
336 DRM_ERROR("timed out waiting for panel to power off\n"); in intel_disable_lvds()
338 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
339 POSTING_READ(lvds_encoder->reg); in intel_disable_lvds()
371 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; in intel_lvds_mode_valid()
372 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; in intel_lvds_mode_valid()
374 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_lvds_mode_valid()
376 if (mode->hdisplay > fixed_mode->hdisplay) in intel_lvds_mode_valid()
378 if (mode->vdisplay > fixed_mode->vdisplay) in intel_lvds_mode_valid()
380 if (fixed_mode->clock > max_pixclk) in intel_lvds_mode_valid()
390 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); in intel_lvds_compute_config()
392 to_lvds_encoder(&intel_encoder->base); in intel_lvds_compute_config()
394 lvds_encoder->attached_connector; in intel_lvds_compute_config()
395 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; in intel_lvds_compute_config()
396 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); in intel_lvds_compute_config()
400 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { in intel_lvds_compute_config()
401 DRM_ERROR("Can't support LVDS on pipe A\n"); in intel_lvds_compute_config()
402 return -EINVAL; in intel_lvds_compute_config()
405 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) in intel_lvds_compute_config()
410 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
411 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", in intel_lvds_compute_config()
412 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
413 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
416 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_lvds_compute_config()
419 * We have timings from the BIOS for the panel, put them in in intel_lvds_compute_config()
421 * with the panel scaling set up to source from the H/VDisplay in intel_lvds_compute_config()
424 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, in intel_lvds_compute_config()
427 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_lvds_compute_config()
428 return -EINVAL; in intel_lvds_compute_config()
431 pipe_config->has_pch_encoder = true; in intel_lvds_compute_config()
434 conn_state->scaling_mode); in intel_lvds_compute_config()
437 conn_state->scaling_mode); in intel_lvds_compute_config()
462 struct drm_device *dev = connector->dev; in intel_lvds_get_modes()
466 if (!IS_ERR_OR_NULL(intel_connector->edid)) in intel_lvds_get_modes()
467 return drm_add_edid_modes(connector, intel_connector->edid); in intel_lvds_get_modes()
469 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode); in intel_lvds_get_modes()
501 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); in intel_no_lvds_dmi_callback()
505 /* These systems claim to have LVDS, but really don't */
525 .ident = "MSI IM-945GSE-A",
552 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
560 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
565 .ident = "AOpen i915GMm-HFS",
568 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
573 .ident = "AOpen i45GMx-I",
576 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
581 .ident = "Aopen i945GTt-VFA",
612 .ident = "Asus AT5NM10T-I",
615 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
620 .ident = "Hewlett-Packard HP t5740",
622 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
628 .ident = "Hewlett-Packard t5745",
630 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
636 .ident = "Hewlett-Packard st5747",
638 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
646 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
647 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
652 .ident = "Gigabyte GA-D525TUD",
660 .ident = "Supermicro X7SPA-H",
663 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
720 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); in intel_dual_link_lvds_callback()
756 for_each_intel_encoder(&dev_priv->drm, encoder) { in intel_get_lvds_encoder()
757 if (encoder->type == INTEL_OUTPUT_LVDS) in intel_get_lvds_encoder()
768 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; in intel_is_dual_link_lvds()
773 struct drm_device *dev = lvds_encoder->base.base.dev; in compute_is_dual_link_lvds()
781 /* single channel LVDS is limited to 112 MHz */ in compute_is_dual_link_lvds()
782 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999) in compute_is_dual_link_lvds()
789 * BIOS should set the proper LVDS register value at boot, but in compute_is_dual_link_lvds()
791 * we need to check "the value to be set" in VBT when LVDS in compute_is_dual_link_lvds()
794 val = I915_READ(lvds_encoder->reg); in compute_is_dual_link_lvds()
800 val = dev_priv->vbt.bios_lvds_val; in compute_is_dual_link_lvds()
806 * intel_lvds_init - setup LVDS connectors on this device
809 * Create the connector, register the LVDS DDC bus, and try to figure out what
810 * modes we can display on the LVDS panel (if present).
814 struct drm_device *dev = &dev_priv->drm; in intel_lvds_init()
824 u32 lvds; in intel_lvds_init() local
828 /* Skip init on machines we know falsely report LVDS */ in intel_lvds_init()
830 WARN(!dev_priv->vbt.int_lvds_support, in intel_lvds_init()
831 "Useless DMI match. Internal LVDS support disabled by VBT\n"); in intel_lvds_init()
835 if (!dev_priv->vbt.int_lvds_support) { in intel_lvds_init()
836 DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n"); in intel_lvds_init()
843 lvds_reg = LVDS; in intel_lvds_init()
845 lvds = I915_READ(lvds_reg); in intel_lvds_init()
848 if ((lvds & LVDS_DETECTED) == 0) in intel_lvds_init()
854 if ((lvds & LVDS_PORT_EN) == 0) { in intel_lvds_init()
855 DRM_DEBUG_KMS("LVDS is not present in VBT\n"); in intel_lvds_init()
858 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); in intel_lvds_init()
871 lvds_encoder->attached_connector = intel_connector; in intel_lvds_init()
873 intel_encoder = &lvds_encoder->base; in intel_lvds_init()
874 encoder = &intel_encoder->base; in intel_lvds_init()
875 connector = &intel_connector->base; in intel_lvds_init()
876 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, in intel_lvds_init()
879 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, in intel_lvds_init()
880 DRM_MODE_ENCODER_LVDS, "LVDS"); in intel_lvds_init()
882 intel_encoder->enable = intel_enable_lvds; in intel_lvds_init()
883 intel_encoder->pre_enable = intel_pre_enable_lvds; in intel_lvds_init()
884 intel_encoder->compute_config = intel_lvds_compute_config; in intel_lvds_init()
886 intel_encoder->disable = pch_disable_lvds; in intel_lvds_init()
887 intel_encoder->post_disable = pch_post_disable_lvds; in intel_lvds_init()
889 intel_encoder->disable = gmch_disable_lvds; in intel_lvds_init()
891 intel_encoder->get_hw_state = intel_lvds_get_hw_state; in intel_lvds_init()
892 intel_encoder->get_config = intel_lvds_get_config; in intel_lvds_init()
893 intel_encoder->update_pipe = intel_panel_update_backlight; in intel_lvds_init()
894 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_lvds_init()
898 intel_encoder->type = INTEL_OUTPUT_LVDS; in intel_lvds_init()
899 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; in intel_lvds_init()
900 intel_encoder->port = PORT_NONE; in intel_lvds_init()
901 intel_encoder->cloneable = 0; in intel_lvds_init()
903 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); in intel_lvds_init()
905 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); in intel_lvds_init()
907 intel_encoder->crtc_mask = (1 << 1); in intel_lvds_init()
910 connector->display_info.subpixel_order = SubPixelHorizontalRGB; in intel_lvds_init()
911 connector->interlace_allowed = false; in intel_lvds_init()
912 connector->doublescan_allowed = false; in intel_lvds_init()
914 lvds_encoder->reg = lvds_reg; in intel_lvds_init()
921 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; in intel_lvds_init()
923 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); in intel_lvds_init()
924 lvds_encoder->init_lvds_val = lvds; in intel_lvds_init()
927 * LVDS discovery: in intel_lvds_init()
930 * 3) check to see if LVDS is already on in intel_lvds_init()
931 * if none of the above, no panel in intel_lvds_init()
935 * Attempt to get the fixed panel mode from DDC. Assume that the in intel_lvds_init()
938 mutex_lock(&dev->mode_config.mutex); in intel_lvds_init()
951 edid = ERR_PTR(-EINVAL); in intel_lvds_init()
954 edid = ERR_PTR(-ENOENT); in intel_lvds_init()
956 intel_connector->edid = edid; in intel_lvds_init()
968 * If we didn't get EDID, try checking if the panel is already turned in intel_lvds_init()
976 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; in intel_lvds_init()
984 mutex_unlock(&dev->mode_config.mutex); in intel_lvds_init()
986 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); in intel_lvds_init()
989 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); in intel_lvds_init()
990 DRM_DEBUG_KMS("detected %s-link lvds configuration\n", in intel_lvds_init()
991 lvds_encoder->is_dual_link ? "dual" : "single"); in intel_lvds_init()
993 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; in intel_lvds_init()
998 mutex_unlock(&dev->mode_config.mutex); in intel_lvds_init()
1000 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); in intel_lvds_init()