81 				     enum transcoder cpu_transcoder)  in assert_hdmi_transcoder_func_disabled()  argument
83 	WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &  in assert_hdmi_transcoder_func_disabled()
167 		 enum transcoder cpu_transcoder,  in hsw_dip_data_reg()  argument
173 		return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);  in hsw_dip_data_reg()
175 		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);  in hsw_dip_data_reg()
177 		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);  in hsw_dip_data_reg()
179 		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);  in hsw_dip_data_reg()
181 		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);  in hsw_dip_data_reg()
183 		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);  in hsw_dip_data_reg()
185 		return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);  in hsw_dip_data_reg()
511 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_write_infoframe()  local
512 	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);  in hsw_write_infoframe()
523 		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,  in hsw_write_infoframe()
529 		I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,  in hsw_write_infoframe()
543 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_read_infoframe()  local
547 	val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder));  in hsw_read_infoframe()
550 		*data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder,  in hsw_read_infoframe()
558 	u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));  in hsw_infoframes_enabled()
959 		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);  in intel_hdmi_set_gcp_infoframe()
984 		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);  in intel_hdmi_read_gcp_infoframe()
1189 	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);  in hsw_set_infoframes()
1193 					     crtc_state->cpu_transcoder);  in hsw_set_infoframes()