Lines Matching refs:pipe

58 	enum pipe pipe;  in ivb_can_enable_err_int()  local
62 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
63 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
75 enum pipe pipe; in cpt_can_enable_serr_int() local
80 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
81 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
93 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
101 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
105 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
106 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
110 enum pipe pipe, in i9xx_set_fifo_underrun_reporting() argument
114 i915_reg_t reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()
119 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i9xx_set_fifo_underrun_reporting()
125 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe)); in i9xx_set_fifo_underrun_reporting()
130 enum pipe pipe, bool enable) in ironlake_set_fifo_underrun_reporting() argument
133 u32 bit = (pipe == PIPE_A) ? in ironlake_set_fifo_underrun_reporting()
145 enum pipe pipe = crtc->pipe; in ivybridge_check_fifo_underruns() local
150 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) in ivybridge_check_fifo_underruns()
153 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivybridge_check_fifo_underruns()
156 trace_intel_cpu_fifo_underrun(dev_priv, pipe); in ivybridge_check_fifo_underruns()
157 DRM_ERROR("fifo underrun on pipe %c\n", pipe_name(pipe)); in ivybridge_check_fifo_underruns()
161 enum pipe pipe, in ivybridge_set_fifo_underrun_reporting() argument
166 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivybridge_set_fifo_underrun_reporting()
176 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivybridge_set_fifo_underrun_reporting()
178 pipe_name(pipe)); in ivybridge_set_fifo_underrun_reporting()
184 enum pipe pipe, bool enable) in broadwell_set_fifo_underrun_reporting() argument
189 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); in broadwell_set_fifo_underrun_reporting()
191 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN); in broadwell_set_fifo_underrun_reporting()
195 enum pipe pch_transcoder, in ibx_set_fifo_underrun_reporting()
211 enum pipe pch_transcoder = crtc->pipe; in cpt_check_pch_fifo_underruns()
228 enum pipe pch_transcoder, in cpt_set_fifo_underrun_reporting()
253 enum pipe pipe, bool enable) in __intel_set_cpu_fifo_underrun_reporting() argument
256 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in __intel_set_cpu_fifo_underrun_reporting()
265 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
267 ironlake_set_fifo_underrun_reporting(dev, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
269 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
271 broadwell_set_fifo_underrun_reporting(dev, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
293 enum pipe pipe, bool enable) in intel_set_cpu_fifo_underrun_reporting() argument
299 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, in intel_set_cpu_fifo_underrun_reporting()
321 enum pipe pch_transcoder, in intel_set_pch_fifo_underrun_reporting()
366 enum pipe pipe) in intel_cpu_fifo_underrun_irq_handler() argument
368 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in intel_cpu_fifo_underrun_irq_handler()
379 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { in intel_cpu_fifo_underrun_irq_handler()
380 trace_intel_cpu_fifo_underrun(dev_priv, pipe); in intel_cpu_fifo_underrun_irq_handler()
382 pipe_name(pipe)); in intel_cpu_fifo_underrun_irq_handler()
398 enum pipe pch_transcoder) in intel_pch_fifo_underrun_irq_handler()