648 	enum pipe pipe = intel_crtc->pipe;  in chv_set_phy_signal_level()  local
655 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_set_phy_signal_level()
659 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_set_phy_signal_level()
662 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_set_phy_signal_level()
666 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_set_phy_signal_level()
669 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));  in chv_set_phy_signal_level()
672 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);  in chv_set_phy_signal_level()
675 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));  in chv_set_phy_signal_level()
678 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);  in chv_set_phy_signal_level()
683 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));  in chv_set_phy_signal_level()
686 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);  in chv_set_phy_signal_level()
691 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));  in chv_set_phy_signal_level()
704 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);  in chv_set_phy_signal_level()
714 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));  in chv_set_phy_signal_level()
719 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);  in chv_set_phy_signal_level()
723 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));  in chv_set_phy_signal_level()
725 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);  in chv_set_phy_signal_level()
728 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));  in chv_set_phy_signal_level()
730 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);  in chv_set_phy_signal_level()
743 	enum pipe pipe = crtc->pipe;  in chv_data_lane_soft_reset()  local
746 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));  in chv_data_lane_soft_reset()
751 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);  in chv_data_lane_soft_reset()
754 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));  in chv_data_lane_soft_reset()
759 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);  in chv_data_lane_soft_reset()
762 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));  in chv_data_lane_soft_reset()
768 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);  in chv_data_lane_soft_reset()
771 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));  in chv_data_lane_soft_reset()
777 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);  in chv_data_lane_soft_reset()
788 	enum pipe pipe = crtc->pipe;  in chv_phy_pre_pll_enable()  local
797 	if (ch == DPIO_CH0 && pipe == PIPE_B)  in chv_phy_pre_pll_enable()
809 	if (pipe != PIPE_B) {  in chv_phy_pre_pll_enable()
810 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_phy_pre_pll_enable()
816 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_phy_pre_pll_enable()
818 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_phy_pre_pll_enable()
824 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_phy_pre_pll_enable()
828 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));  in chv_phy_pre_pll_enable()
830 	if (pipe != PIPE_B)  in chv_phy_pre_pll_enable()
834 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);  in chv_phy_pre_pll_enable()
837 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));  in chv_phy_pre_pll_enable()
839 		if (pipe != PIPE_B)  in chv_phy_pre_pll_enable()
843 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);  in chv_phy_pre_pll_enable()
851 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));  in chv_phy_pre_pll_enable()
852 	if (pipe != PIPE_B)  in chv_phy_pre_pll_enable()
856 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);  in chv_phy_pre_pll_enable()
869 	enum pipe pipe = crtc->pipe;  in chv_phy_pre_encoder_enable()  local
876 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_phy_pre_encoder_enable()
878 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_phy_pre_encoder_enable()
881 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_phy_pre_encoder_enable()
883 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_phy_pre_encoder_enable()
893 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),  in chv_phy_pre_encoder_enable()
909 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));  in chv_phy_pre_encoder_enable()
911 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);  in chv_phy_pre_encoder_enable()
914 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));  in chv_phy_pre_encoder_enable()
916 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);  in chv_phy_pre_encoder_enable()
919 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),  in chv_phy_pre_encoder_enable()
927 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),  in chv_phy_pre_encoder_enable()
956 	enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;  in chv_phy_post_pll_disable()  local
962 	if (pipe != PIPE_B) {  in chv_phy_post_pll_disable()
963 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_phy_post_pll_disable()
965 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);  in chv_phy_post_pll_disable()
967 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_phy_post_pll_disable()
969 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);  in chv_phy_post_pll_disable()
994 	enum pipe pipe = intel_crtc->pipe;  in vlv_set_phy_signal_level()  local
998 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);  in vlv_set_phy_signal_level()
999 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);  in vlv_set_phy_signal_level()
1000 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),  in vlv_set_phy_signal_level()
1002 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);  in vlv_set_phy_signal_level()
1005 		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);  in vlv_set_phy_signal_level()
1007 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);  in vlv_set_phy_signal_level()
1008 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);  in vlv_set_phy_signal_level()
1009 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);  in vlv_set_phy_signal_level()
1021 	enum pipe pipe = crtc->pipe;  in vlv_phy_pre_pll_enable()  local
1026 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),  in vlv_phy_pre_pll_enable()
1029 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),  in vlv_phy_pre_pll_enable()
1036 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);  in vlv_phy_pre_pll_enable()
1037 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);  in vlv_phy_pre_pll_enable()
1038 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);  in vlv_phy_pre_pll_enable()
1051 	enum pipe pipe = crtc->pipe;  in vlv_phy_pre_encoder_enable()  local
1057 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));  in vlv_phy_pre_encoder_enable()
1059 	if (pipe)  in vlv_phy_pre_encoder_enable()
1064 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);  in vlv_phy_pre_encoder_enable()
1067 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);  in vlv_phy_pre_encoder_enable()
1068 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);  in vlv_phy_pre_encoder_enable()
1080 	enum pipe pipe = crtc->pipe;  in vlv_phy_reset_lanes()  local
1083 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);  in vlv_phy_reset_lanes()
1084 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);  in vlv_phy_reset_lanes()