Lines Matching refs:val
271 u32 val; in bxt_ddi_phy_set_signal_level() local
281 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
282 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); in bxt_ddi_phy_set_signal_level()
283 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
285 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
286 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); in bxt_ddi_phy_set_signal_level()
287 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; in bxt_ddi_phy_set_signal_level()
288 I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
290 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
291 val &= ~SCALE_DCOMP_METHOD; in bxt_ddi_phy_set_signal_level()
293 val |= SCALE_DCOMP_METHOD; in bxt_ddi_phy_set_signal_level()
295 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) in bxt_ddi_phy_set_signal_level()
298 I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
300 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
301 val &= ~DE_EMPHASIS; in bxt_ddi_phy_set_signal_level()
302 val |= deemphasis << DEEMPH_SHIFT; in bxt_ddi_phy_set_signal_level()
303 I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
305 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
306 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; in bxt_ddi_phy_set_signal_level()
307 I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val); in bxt_ddi_phy_set_signal_level()
340 u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); in bxt_get_grc() local
342 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; in bxt_get_grc()
357 u32 val; in _bxt_ddi_phy_init() local
376 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
377 val |= phy_info->pwron_mask; in _bxt_ddi_phy_init()
378 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in _bxt_ddi_phy_init()
396 val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); in _bxt_ddi_phy_init()
397 val &= ~IREF0RC_OFFSET_MASK; in _bxt_ddi_phy_init()
398 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; in _bxt_ddi_phy_init()
399 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); in _bxt_ddi_phy_init()
401 val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); in _bxt_ddi_phy_init()
402 val &= ~IREF1RC_OFFSET_MASK; in _bxt_ddi_phy_init()
403 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; in _bxt_ddi_phy_init()
404 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); in _bxt_ddi_phy_init()
407 val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); in _bxt_ddi_phy_init()
408 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | in _bxt_ddi_phy_init()
410 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); in _bxt_ddi_phy_init()
413 val = I915_READ(BXT_PORT_CL2CM_DW6(phy)); in _bxt_ddi_phy_init()
414 val |= DW6_OLDO_DYN_PWR_DOWN_EN; in _bxt_ddi_phy_init()
415 I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val); in _bxt_ddi_phy_init()
428 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, in _bxt_ddi_phy_init()
430 grc_code = val << GRC_CODE_FAST_SHIFT | in _bxt_ddi_phy_init()
431 val << GRC_CODE_SLOW_SHIFT | in _bxt_ddi_phy_init()
432 val; in _bxt_ddi_phy_init()
435 val = I915_READ(BXT_PORT_REF_DW8(phy)); in _bxt_ddi_phy_init()
436 val |= GRC_DIS | GRC_RDY_OVRD; in _bxt_ddi_phy_init()
437 I915_WRITE(BXT_PORT_REF_DW8(phy), val); in _bxt_ddi_phy_init()
443 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); in _bxt_ddi_phy_init()
444 val |= COMMON_RESET_DIS; in _bxt_ddi_phy_init()
445 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); in _bxt_ddi_phy_init()
451 u32 val; in bxt_ddi_phy_uninit() local
455 val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); in bxt_ddi_phy_uninit()
456 val &= ~COMMON_RESET_DIS; in bxt_ddi_phy_uninit()
457 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); in bxt_ddi_phy_uninit()
459 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in bxt_ddi_phy_uninit()
460 val &= ~phy_info->pwron_mask; in bxt_ddi_phy_uninit()
461 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); in bxt_ddi_phy_uninit()
497 u32 val; in __phy_reg_verify_state() local
499 val = I915_READ(reg); in __phy_reg_verify_state()
500 if ((val & mask) == expected) in __phy_reg_verify_state()
509 phy, &vaf, reg.reg, val, (val & ~mask) | expected, in __phy_reg_verify_state()
602 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_set_lane_optim_mask() local
608 val &= ~LATENCY_OPTIM; in bxt_ddi_phy_set_lane_optim_mask()
610 val |= LATENCY_OPTIM; in bxt_ddi_phy_set_lane_optim_mask()
612 I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val); in bxt_ddi_phy_set_lane_optim_mask()
630 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_ddi_phy_get_lane_lat_optim_mask() local
632 if (val & LATENCY_OPTIM) in bxt_ddi_phy_get_lane_lat_optim_mask()
649 u32 val; in chv_set_phy_signal_level() local
655 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
656 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); in chv_set_phy_signal_level()
657 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); in chv_set_phy_signal_level()
658 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; in chv_set_phy_signal_level()
659 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
662 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
663 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); in chv_set_phy_signal_level()
664 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); in chv_set_phy_signal_level()
665 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; in chv_set_phy_signal_level()
666 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
669 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
670 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); in chv_set_phy_signal_level()
671 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; in chv_set_phy_signal_level()
672 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
675 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
676 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); in chv_set_phy_signal_level()
677 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; in chv_set_phy_signal_level()
678 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
683 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
684 val &= ~DPIO_SWING_DEEMPH9P5_MASK; in chv_set_phy_signal_level()
685 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; in chv_set_phy_signal_level()
686 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in chv_set_phy_signal_level()
691 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); in chv_set_phy_signal_level()
693 val &= ~DPIO_SWING_MARGIN000_MASK; in chv_set_phy_signal_level()
694 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; in chv_set_phy_signal_level()
701 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); in chv_set_phy_signal_level()
702 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; in chv_set_phy_signal_level()
704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in chv_set_phy_signal_level()
714 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); in chv_set_phy_signal_level()
716 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; in chv_set_phy_signal_level()
718 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; in chv_set_phy_signal_level()
719 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in chv_set_phy_signal_level()
723 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
724 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; in chv_set_phy_signal_level()
725 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
728 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
729 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; in chv_set_phy_signal_level()
730 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
744 u32 val; in chv_data_lane_soft_reset() local
746 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_data_lane_soft_reset()
748 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); in chv_data_lane_soft_reset()
750 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; in chv_data_lane_soft_reset()
751 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_data_lane_soft_reset()
754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_data_lane_soft_reset()
756 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); in chv_data_lane_soft_reset()
758 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; in chv_data_lane_soft_reset()
759 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_data_lane_soft_reset()
762 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_data_lane_soft_reset()
763 val |= CHV_PCS_REQ_SOFTRESET_EN; in chv_data_lane_soft_reset()
765 val &= ~DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
767 val |= DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
768 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_data_lane_soft_reset()
771 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_data_lane_soft_reset()
772 val |= CHV_PCS_REQ_SOFTRESET_EN; in chv_data_lane_soft_reset()
774 val &= ~DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
776 val |= DPIO_PCS_CLK_SOFT_RESET; in chv_data_lane_soft_reset()
777 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_data_lane_soft_reset()
791 u32 val; in chv_phy_pre_pll_enable() local
810 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_pre_pll_enable()
811 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); in chv_phy_pre_pll_enable()
813 val |= CHV_BUFLEFTENA1_FORCE; in chv_phy_pre_pll_enable()
815 val |= CHV_BUFRIGHTENA1_FORCE; in chv_phy_pre_pll_enable()
816 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_phy_pre_pll_enable()
818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_phy_pre_pll_enable()
819 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); in chv_phy_pre_pll_enable()
821 val |= CHV_BUFLEFTENA2_FORCE; in chv_phy_pre_pll_enable()
823 val |= CHV_BUFRIGHTENA2_FORCE; in chv_phy_pre_pll_enable()
824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_phy_pre_pll_enable()
828 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_phy_pre_pll_enable()
829 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; in chv_phy_pre_pll_enable()
831 val &= ~CHV_PCS_USEDCLKCHANNEL; in chv_phy_pre_pll_enable()
833 val |= CHV_PCS_USEDCLKCHANNEL; in chv_phy_pre_pll_enable()
834 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_phy_pre_pll_enable()
837 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_phy_pre_pll_enable()
838 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; in chv_phy_pre_pll_enable()
840 val &= ~CHV_PCS_USEDCLKCHANNEL; in chv_phy_pre_pll_enable()
842 val |= CHV_PCS_USEDCLKCHANNEL; in chv_phy_pre_pll_enable()
843 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_phy_pre_pll_enable()
851 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_phy_pre_pll_enable()
853 val &= ~CHV_CMN_USEDCLKCHANNEL; in chv_phy_pre_pll_enable()
855 val |= CHV_CMN_USEDCLKCHANNEL; in chv_phy_pre_pll_enable()
856 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_phy_pre_pll_enable()
871 u32 val; in chv_phy_pre_encoder_enable() local
876 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_phy_pre_encoder_enable()
877 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; in chv_phy_pre_encoder_enable()
878 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_phy_pre_encoder_enable()
881 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_phy_pre_encoder_enable()
882 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; in chv_phy_pre_encoder_enable()
883 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_phy_pre_encoder_enable()
909 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_phy_pre_encoder_enable()
910 val |= DPIO_TX2_STAGGER_MASK(0x1f); in chv_phy_pre_encoder_enable()
911 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_phy_pre_encoder_enable()
914 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_phy_pre_encoder_enable()
915 val |= DPIO_TX2_STAGGER_MASK(0x1f); in chv_phy_pre_encoder_enable()
916 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_phy_pre_encoder_enable()
957 u32 val; in chv_phy_post_pll_disable() local
963 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_phy_post_pll_disable()
964 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); in chv_phy_post_pll_disable()
965 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_phy_post_pll_disable()
967 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_phy_post_pll_disable()
968 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); in chv_phy_post_pll_disable()
969 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_phy_post_pll_disable()
1052 u32 val; in vlv_phy_pre_encoder_enable() local
1057 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_phy_pre_encoder_enable()
1058 val = 0; in vlv_phy_pre_encoder_enable()
1060 val |= (1<<21); in vlv_phy_pre_encoder_enable()
1062 val &= ~(1<<21); in vlv_phy_pre_encoder_enable()
1063 val |= 0x001000c4; in vlv_phy_pre_encoder_enable()
1064 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_phy_pre_encoder_enable()