3880 	u32 signal_levels = 0;  in g4x_signal_levels()  local
3885 		signal_levels |= DP_VOLTAGE_0_4;  in g4x_signal_levels()
3888 		signal_levels |= DP_VOLTAGE_0_6;  in g4x_signal_levels()
3891 		signal_levels |= DP_VOLTAGE_0_8;  in g4x_signal_levels()
3894 		signal_levels |= DP_VOLTAGE_1_2;  in g4x_signal_levels()
3900 		signal_levels |= DP_PRE_EMPHASIS_0;  in g4x_signal_levels()
3903 		signal_levels |= DP_PRE_EMPHASIS_3_5;  in g4x_signal_levels()
3906 		signal_levels |= DP_PRE_EMPHASIS_6;  in g4x_signal_levels()
3909 		signal_levels |= DP_PRE_EMPHASIS_9_5;  in g4x_signal_levels()
3912 	return signal_levels;  in g4x_signal_levels()
3919 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in snb_cpu_edp_signal_levels()  local
3921 	switch (signal_levels) {  in snb_cpu_edp_signal_levels()
3938 			      "0x%x\n", signal_levels);  in snb_cpu_edp_signal_levels()
3947 	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |  in ivb_cpu_edp_signal_levels()  local
3949 	switch (signal_levels) {  in ivb_cpu_edp_signal_levels()
3969 			      "0x%x\n", signal_levels);  in ivb_cpu_edp_signal_levels()
3980 	u32 signal_levels, mask = 0;  in intel_dp_set_signal_levels()  local
3984 		signal_levels = bxt_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3986 		signal_levels = ddi_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3989 		signal_levels = chv_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3991 		signal_levels = vlv_signal_levels(intel_dp);  in intel_dp_set_signal_levels()
3993 		signal_levels = ivb_cpu_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3996 		signal_levels = snb_cpu_edp_signal_levels(train_set);  in intel_dp_set_signal_levels()
3999 		signal_levels = g4x_signal_levels(train_set);  in intel_dp_set_signal_levels()
4004 		DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);  in intel_dp_set_signal_levels()
4012 	intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;  in intel_dp_set_signal_levels()