984 	if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&  in intel_power_sequencer_reset()
1031 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_pps_get_registers()
1080 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in edp_notify_handler()
1106 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in edp_have_panel_power()
1119 	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in edp_have_panel_vdd()
1743 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_set_clock()
3425 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_enable_dp()
3435 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_enable_dp()
3652 	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_voltage_max()
3671 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_pre_emphasis_max()
3990 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_set_signal_levels()
4125 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_link_down()
6228 	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&  in intel_dp_encoder_reset()
6233 		if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_encoder_reset()
6575 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_init_panel_power_sequencer_registers()
6627 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_dp_pps_init()
6709 			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_set_drrs_state()
6714 			if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_set_drrs_state()
7069 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {  in intel_edp_init_connector()
7178 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))  in intel_dp_init_connector()
7190 	if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&  in intel_dp_init_connector()
7296 	} else if (IS_VALLEYVIEW(dev_priv)) {  in intel_dp_init()