1021 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,  in intel_pipe_to_cpu_transcoder()
1076 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_wait_for_pipe_off()
1122 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,  in assert_fdi_tx()
1246 	enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,  in assert_pipe()
1678 				      enum transcoder cpu_transcoder)  in lpt_enable_pch_transcoder()
1797 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in intel_enable_pipe()
1855 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_disable_pipe()
5112 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ironlake_pch_transcoder_set_timings()
5301 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in lpt_pch_enable()
6446 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in haswell_crtc_enable()
6629 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in haswell_crtc_disable()
6795 	enum transcoder transcoder = crtc_state->cpu_transcoder;  in get_crtc_power_domains()  local
6801 	mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(transcoder));  in get_crtc_power_domains()
7633 				 enum transcoder transcoder)  in transcoder_has_m2_n2()  argument
7636 		return transcoder == TRANSCODER_EDP;  in transcoder_has_m2_n2()
7652 	enum transcoder transcoder = crtc_state->cpu_transcoder;  in intel_cpu_transcoder_set_m_n()  local
7655 		I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);  in intel_cpu_transcoder_set_m_n()
7656 		I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);  in intel_cpu_transcoder_set_m_n()
7657 		I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);  in intel_cpu_transcoder_set_m_n()
7658 		I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);  in intel_cpu_transcoder_set_m_n()
7664 		    transcoder_has_m2_n2(dev_priv, transcoder)) {  in intel_cpu_transcoder_set_m_n()
7665 			I915_WRITE(PIPE_DATA_M2(transcoder),  in intel_cpu_transcoder_set_m_n()
7667 			I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);  in intel_cpu_transcoder_set_m_n()
7668 			I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);  in intel_cpu_transcoder_set_m_n()
7669 			I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);  in intel_cpu_transcoder_set_m_n()
8125 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_pipe_timings()
8201 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_get_pipe_timings()
8781 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in i9xx_get_pipe_config()
9435 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in haswell_set_pipeconf()
9706 					 enum transcoder transcoder,  in intel_cpu_transcoder_get_m_n()  argument
9714 		m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));  in intel_cpu_transcoder_get_m_n()
9715 		m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));  in intel_cpu_transcoder_get_m_n()
9716 		m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))  in intel_cpu_transcoder_get_m_n()
9718 		m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));  in intel_cpu_transcoder_get_m_n()
9719 		m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))  in intel_cpu_transcoder_get_m_n()
9722 		if (m2_n2 && transcoder_has_m2_n2(dev_priv, transcoder)) {  in intel_cpu_transcoder_get_m_n()
9723 			m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));  in intel_cpu_transcoder_get_m_n()
9724 			m2_n2->link_n =	I915_READ(PIPE_LINK_N2(transcoder));  in intel_cpu_transcoder_get_m_n()
9725 			m2_n2->gmch_m =	I915_READ(PIPE_DATA_M2(transcoder))  in intel_cpu_transcoder_get_m_n()
9727 			m2_n2->gmch_n =	I915_READ(PIPE_DATA_N2(transcoder));  in intel_cpu_transcoder_get_m_n()
9728 			m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))  in intel_cpu_transcoder_get_m_n()
9958 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in ironlake_get_pipe_config()
10210 	enum transcoder panel_transcoder;  in hsw_get_transcoder_state()
10225 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in hsw_get_transcoder_state()
10304 	enum transcoder cpu_transcoder;  in bxt_get_dsi_transcoder_state()
12290 		(enum transcoder) to_intel_crtc(crtc)->pipe;  in intel_modeset_pipe_config()
16440 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_sanitize_crtc()
17196 		enum transcoder cpu_transcoder;
17206 	} transcoder[5];  member
17222 	BUILD_BUG_ON(ARRAY_SIZE(transcoders) != ARRAY_SIZE(error->transcoder));  in intel_display_capture_error_state()
17264 	for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {  in intel_display_capture_error_state()
17265 		enum transcoder cpu_transcoder = transcoders[i];  in intel_display_capture_error_state()
17270 		error->transcoder[i].available = true;  in intel_display_capture_error_state()
17271 		error->transcoder[i].power_domain_on =  in intel_display_capture_error_state()
17274 		if (!error->transcoder[i].power_domain_on)  in intel_display_capture_error_state()
17277 		error->transcoder[i].cpu_transcoder = cpu_transcoder;  in intel_display_capture_error_state()
17279 		error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));  in intel_display_capture_error_state()
17280 		error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));  in intel_display_capture_error_state()
17281 		error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));  in intel_display_capture_error_state()
17282 		error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));  in intel_display_capture_error_state()
17283 		error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));  in intel_display_capture_error_state()
17284 		error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));  in intel_display_capture_error_state()
17285 		error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));  in intel_display_capture_error_state()
17334 	for (i = 0; i < ARRAY_SIZE(error->transcoder); i++) {  in intel_display_print_error_state()
17335 		if (!error->transcoder[i].available)  in intel_display_print_error_state()
17339 			   transcoder_name(error->transcoder[i].cpu_transcoder));  in intel_display_print_error_state()
17341 			   onoff(error->transcoder[i].power_domain_on));  in intel_display_print_error_state()
17342 		err_printf(m, "  CONF: %08x\n", error->transcoder[i].conf);  in intel_display_print_error_state()
17343 		err_printf(m, "  HTOTAL: %08x\n", error->transcoder[i].htotal);  in intel_display_print_error_state()
17344 		err_printf(m, "  HBLANK: %08x\n", error->transcoder[i].hblank);  in intel_display_print_error_state()
17345 		err_printf(m, "  HSYNC: %08x\n", error->transcoder[i].hsync);  in intel_display_print_error_state()
17346 		err_printf(m, "  VTOTAL: %08x\n", error->transcoder[i].vtotal);  in intel_display_print_error_state()
17347 		err_printf(m, "  VBLANK: %08x\n", error->transcoder[i].vblank);  in intel_display_print_error_state()
17348 		err_printf(m, "  VSYNC: %08x\n", error->transcoder[i].vsync);  in intel_display_print_error_state()