7275 					   pipe_config->pipe_bpp);  in ironlake_fdi_compute_config()
7279 	intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,  in ironlake_fdi_compute_config()
7286 	if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {  in ironlake_fdi_compute_config()
7287 		pipe_config->pipe_bpp -= 2*3;  in ironlake_fdi_compute_config()
7289 			      pipe_config->pipe_bpp);  in ironlake_fdi_compute_config()
7314 	if (crtc_state->pipe_bpp > 24)  in hsw_crtc_state_ips_capable()
8298 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
8302 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
8794 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
8797 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
8800 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
9396 	switch (crtc_state->pipe_bpp) {  in ironlake_set_pipeconf()
9456 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipemisc()
9470 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipemisc()
9968 		pipe_config->pipe_bpp = 18;  in ironlake_get_pipe_config()
9971 		pipe_config->pipe_bpp = 24;  in ironlake_get_pipe_config()
9974 		pipe_config->pipe_bpp = 30;  in ironlake_get_pipe_config()
9977 		pipe_config->pipe_bpp = 36;  in ironlake_get_pipe_config()
11903 	if (bpp < pipe_config->pipe_bpp) {  in compute_sink_pipe_bpp()
11908 			      pipe_config->pipe_bpp);  in compute_sink_pipe_bpp()
11910 		pipe_config->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
11934 	pipe_config->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
12096 		      pipe_config->pipe_bpp, pipe_config->dither);  in intel_dump_pipe_config()
12310 	base_bpp = pipe_config->pipe_bpp;  in intel_modeset_pipe_config()
12402 	pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
12405 		      base_bpp, pipe_config->pipe_bpp, pipe_config->dither);  in intel_modeset_pipe_config()
12831 		PIPE_CONF_CHECK_I(pipe_bpp);  in intel_pipe_config_compare()