Lines Matching refs:dpll
533 static int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
545 static u32 i9xx_dpll_compute_m(struct dpll *dpll) in i9xx_dpll_compute_m() argument
547 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
550 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
562 static int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
574 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
595 const struct dpll *clock) in intel_PLL_is_valid()
668 int target, int refclk, struct dpll *match_clock, in i9xx_find_best_dpll()
669 struct dpll *best_clock) in i9xx_find_best_dpll()
672 struct dpll clock; in i9xx_find_best_dpll()
726 int target, int refclk, struct dpll *match_clock, in pnv_find_best_dpll()
727 struct dpll *best_clock) in pnv_find_best_dpll()
730 struct dpll clock; in pnv_find_best_dpll()
782 int target, int refclk, struct dpll *match_clock, in g4x_find_best_dpll()
783 struct dpll *best_clock) in g4x_find_best_dpll()
786 struct dpll clock; in g4x_find_best_dpll()
833 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
834 const struct dpll *best_clock, in vlv_PLL_is_optimal()
876 int target, int refclk, struct dpll *match_clock, in vlv_find_best_dpll()
877 struct dpll *best_clock) in vlv_find_best_dpll()
881 struct dpll clock; in vlv_find_best_dpll()
936 int target, int refclk, struct dpll *match_clock, in chv_find_best_dpll()
937 struct dpll *best_clock) in chv_find_best_dpll()
942 struct dpll clock; in chv_find_best_dpll()
992 struct dpll *best_clock) in bxt_find_best_dpll()
1381 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1400 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in vlv_enable_pll()
1431 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1449 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) in chv_enable_pll()
1488 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1502 I915_WRITE(reg, dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1503 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1518 I915_WRITE(reg, dpll); in i9xx_enable_pll()
1523 I915_WRITE(reg, dpll); in i9xx_enable_pll()
7553 static u32 pnv_dpll_compute_fp(struct dpll *dpll) in pnv_dpll_compute_fp() argument
7555 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
7558 static u32 i9xx_dpll_compute_fp(struct dpll *dpll) in i9xx_dpll_compute_fp() argument
7560 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
7565 struct dpll *reduced_clock) in i9xx_update_pll_dividers()
7571 fp = pnv_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
7575 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in i9xx_update_pll_dividers()
7707 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
7710 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
7714 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
7724 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
7727 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
7731 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
7749 pipe_config->dpll_hw_state.dpll & in vlv_prepare_pll()
7753 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_prepare_pll()
7758 bestn = pipe_config->dpll.n; in vlv_prepare_pll()
7759 bestm1 = pipe_config->dpll.m1; in vlv_prepare_pll()
7760 bestm2 = pipe_config->dpll.m2; in vlv_prepare_pll()
7761 bestp1 = pipe_config->dpll.p1; in vlv_prepare_pll()
7762 bestp2 = pipe_config->dpll.p2; in vlv_prepare_pll()
7851 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_prepare_pll()
7854 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_prepare_pll()
7857 bestn = pipe_config->dpll.n; in chv_prepare_pll()
7858 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; in chv_prepare_pll()
7859 bestm1 = pipe_config->dpll.m1; in chv_prepare_pll()
7860 bestm2 = pipe_config->dpll.m2 >> 22; in chv_prepare_pll()
7861 bestp1 = pipe_config->dpll.p1; in chv_prepare_pll()
7862 bestp2 = pipe_config->dpll.p2; in chv_prepare_pll()
7863 vco = pipe_config->dpll.vco; in chv_prepare_pll()
7953 const struct dpll *dpll) in vlv_force_pll_on() argument
7964 pipe_config->dpll = *dpll; in vlv_force_pll_on()
7999 struct dpll *reduced_clock) in i9xx_compute_dpll()
8002 u32 dpll; in i9xx_compute_dpll() local
8003 struct dpll *clock = &crtc_state->dpll; in i9xx_compute_dpll()
8007 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
8010 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
8012 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
8016 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
8022 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
8025 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
8029 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
8031 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
8033 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
8037 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
8040 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
8043 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
8046 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
8050 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
8053 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
8056 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
8058 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
8060 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
8061 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
8072 struct dpll *reduced_clock) in i8xx_compute_dpll()
8076 u32 dpll; in i8xx_compute_dpll() local
8077 struct dpll *clock = &crtc_state->dpll; in i8xx_compute_dpll()
8081 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
8084 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
8087 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
8089 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
8091 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
8108 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
8112 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
8114 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
8116 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
8117 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
8364 refclk, NULL, &crtc_state->dpll)) { in i8xx_crtc_compute_clock()
8406 refclk, NULL, &crtc_state->dpll)) { in g4x_crtc_compute_clock()
8440 refclk, NULL, &crtc_state->dpll)) { in pnv_crtc_compute_clock()
8474 refclk, NULL, &crtc_state->dpll)) { in i9xx_crtc_compute_clock()
8495 refclk, NULL, &crtc_state->dpll)) { in chv_crtc_compute_clock()
8516 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
8567 struct dpll clock; in vlv_crtc_clock_get()
8572 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
8678 struct dpll clock; in chv_crtc_clock_get()
8683 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
8850 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8856 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
9526 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) in ironlake_needs_fb_cb_tune() argument
9528 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; in ironlake_needs_fb_cb_tune()
9533 struct dpll *reduced_clock) in ironlake_compute_dpll()
9536 u32 dpll, fp, fp2; in ironlake_compute_dpll() local
9551 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); in ironlake_compute_dpll()
9553 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) in ironlake_compute_dpll()
9565 dpll = 0; in ironlake_compute_dpll()
9568 dpll |= DPLLB_MODE_LVDS; in ironlake_compute_dpll()
9570 dpll |= DPLLB_MODE_DAC_SERIAL; in ironlake_compute_dpll()
9572 dpll |= (crtc_state->pixel_multiplier - 1) in ironlake_compute_dpll()
9577 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
9580 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
9598 dpll |= DPLL_SDVO_HIGH_SPEED; in ironlake_compute_dpll()
9601 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
9603 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ironlake_compute_dpll()
9605 switch (crtc_state->dpll.p2) { in ironlake_compute_dpll()
9607 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ironlake_compute_dpll()
9610 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ironlake_compute_dpll()
9613 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ironlake_compute_dpll()
9616 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ironlake_compute_dpll()
9622 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ironlake_compute_dpll()
9624 dpll |= PLL_REF_INPUT_DREFCLK; in ironlake_compute_dpll()
9626 dpll |= DPLL_VCO_ENABLE; in ironlake_compute_dpll()
9628 crtc_state->dpll_hw_state.dpll = dpll; in ironlake_compute_dpll()
9673 refclk, NULL, &crtc_state->dpll)) { in ironlake_crtc_compute_clock()
10027 tmp = pipe_config->dpll_hw_state.dpll; in ironlake_get_pipe_config()
11271 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk() local
11273 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) in i9xx_pll_refclk()
11290 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get() local
11292 struct dpll clock; in i9xx_crtc_clock_get()
11296 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) in i9xx_crtc_clock_get()
11312 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
11315 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
11318 switch (dpll & DPLL_MODE_MASK) { in i9xx_crtc_clock_get()
11320 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? in i9xx_crtc_clock_get()
11324 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? in i9xx_crtc_clock_get()
11329 "mode\n", (int)(dpll & DPLL_MODE_MASK)); in i9xx_crtc_clock_get()
11342 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
11350 if (dpll & PLL_P1_DIVIDE_BY_TWO) in i9xx_crtc_clock_get()
11353 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
11356 if (dpll & PLL_P2_DIVIDE_BY_4) in i9xx_crtc_clock_get()
12795 PIPE_CONF_CHECK_X(dpll_hw_state.dpll); in intel_pipe_config_compare()
16289 struct dpll clock = { in i830_enable_pipe()
16296 u32 dpll, fp; in i830_enable_pipe() local
16305 dpll = DPLL_DVO_2X_MODE | in i830_enable_pipe()
16328 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i830_enable_pipe()
16329 I915_WRITE(DPLL(pipe), dpll); in i830_enable_pipe()
16340 I915_WRITE(DPLL(pipe), dpll); in i830_enable_pipe()
16344 I915_WRITE(DPLL(pipe), dpll); in i830_enable_pipe()