3703 	if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {  in i9xx_check_plane_surface()
3821 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in i9xx_update_plane()
5659 		if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))  in ironlake_pfit_enable()
5832 	if (IS_HASWELL(dev_priv) &&  in hsw_pre_update_disable_ips()
5859 	if (IS_HASWELL(dev_priv) &&  in hsw_post_update_enable_ips()
6543 	if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {  in haswell_crtc_enable()
7197 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in ironlake_check_fdi_lanes()
7635 	if (IS_HASWELL(dev_priv))  in transcoder_has_m2_n2()
8176 	if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&  in intel_set_pipe_timings()
8638 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in i9xx_get_initial_plane_config()
9438 	if (IS_HASWELL(dev_priv) && crtc_state->dither)  in haswell_set_pipeconf()
10476 		if (IS_HASWELL(dev_priv))  in haswell_get_pipe_config()
12734 	if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||  in intel_pipe_config_compare()
13560 	if (IS_HASWELL(dev_priv))  in intel_modeset_checks()
14828 	if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))  in i9xx_plane_has_fbc()
15796 	    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {  in intel_mode_valid()
15923 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {  in intel_init_display_hooks()
16868 	if (IS_HASWELL(dev_priv)) {  in intel_early_display_was()
17231 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_display_capture_error_state()
17251 		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))  in intel_display_capture_error_state()
17304 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_display_print_error_state()
17321 		if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))  in intel_display_print_error_state()