1275 static int skl_calc_wrpll_link(const struct intel_dpll_hw_state *pll_state)  in skl_calc_wrpll_link()  argument
1279 	p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;  in skl_calc_wrpll_link()
1280 	p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;  in skl_calc_wrpll_link()
1282 	if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))  in skl_calc_wrpll_link()
1283 		p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;  in skl_calc_wrpll_link()
1318 	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK)  in skl_calc_wrpll_link()
1321 	dco_freq += (((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9)  in skl_calc_wrpll_link()
1331 			struct intel_dpll_hw_state *pll_state)  in cnl_calc_wrpll_link()  argument
1335 	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;  in cnl_calc_wrpll_link()
1336 	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;  in cnl_calc_wrpll_link()
1338 	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))  in cnl_calc_wrpll_link()
1339 		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>  in cnl_calc_wrpll_link()
1374 	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK)  in cnl_calc_wrpll_link()
1377 	dco_freq += (((pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>  in cnl_calc_wrpll_link()
1409 				const struct intel_dpll_hw_state *pll_state)  in icl_calc_mg_pll_link()  argument
1416 	m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;  in icl_calc_mg_pll_link()
1417 	m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;  in icl_calc_mg_pll_link()
1418 	m2_frac = (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ?  in icl_calc_mg_pll_link()
1419 		(pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >>  in icl_calc_mg_pll_link()
1422 	switch (pll_state->mg_clktop2_hsclkctl &  in icl_calc_mg_pll_link()
1437 		MISSING_CASE(pll_state->mg_clktop2_hsclkctl);  in icl_calc_mg_pll_link()
1441 	div2 = (pll_state->mg_clktop2_hsclkctl &  in icl_calc_mg_pll_link()
1489 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;  in icl_ddi_clock_get()  local
1495 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);  in icl_ddi_clock_get()
1503 			link_clock = icl_calc_mg_pll_link(dev_priv, pll_state);  in icl_ddi_clock_get()
1515 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;  in cnl_ddi_clock_get()  local
1518 	if (pll_state->cfgcr0 & DPLL_CFGCR0_HDMI_MODE) {  in cnl_ddi_clock_get()
1519 		link_clock = cnl_calc_wrpll_link(dev_priv, pll_state);  in cnl_ddi_clock_get()
1521 		link_clock = pll_state->cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK;  in cnl_ddi_clock_get()
1563 	struct intel_dpll_hw_state *pll_state = &pipe_config->dpll_hw_state;  in skl_ddi_clock_get()  local
1570 	if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0)) {  in skl_ddi_clock_get()
1571 		link_clock = skl_calc_wrpll_link(pll_state);  in skl_ddi_clock_get()
1573 		link_clock = pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0);  in skl_ddi_clock_get()
1654 static int bxt_calc_pll_link(const struct intel_dpll_hw_state *pll_state)  in bxt_calc_pll_link()  argument
1659 	clock.m2 = (pll_state->pll0 & PORT_PLL_M2_MASK) << 22;  in bxt_calc_pll_link()
1660 	if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)  in bxt_calc_pll_link()
1661 		clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK;  in bxt_calc_pll_link()
1662 	clock.n = (pll_state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;  in bxt_calc_pll_link()
1663 	clock.p1 = (pll_state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;  in bxt_calc_pll_link()
1664 	clock.p2 = (pll_state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;  in bxt_calc_pll_link()